18.2.2011 PB171 Spring 2011 1
PIC MicrocontrollerPIC Microcontroller
IntroductionIntroduction
Vojtěch KrmíčekVojtěch Krmíček
vojtec@ics.muni.czvojtec@ics.muni.cz
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Microcontroller IMicrocontroller I
AAlso MCU or µClso MCU or µC
CComputer-on-a-chipomputer-on-a-chip
– microprocessormicroprocessor
– high integrationhigh integration
– low power consumptionlow power consumption
– self-sufficiency and cost-self-sufficiency and cost-
effectivenesseffectiveness
UsuallyUsually integrates additionalintegrates additional
elementselements
– read-write memory for dataread-write memory for data
storagestorage
– read-only memory, such asread-only memory, such as
flash for code storageflash for code storage
– EEPROM for permanent dataEEPROM for permanent data
storagestorage
– peripheral devicesperipheral devices andand
input/output interfacesinput/output interfaces
CClock speeds oflock speeds of a few MHza few MHz,,
but this is adequate for typicalbut this is adequate for typical
applicationsapplications
FFrequently used inrequently used in
automatically controlledautomatically controlled
products and devicesproducts and devices
– automobile engine controlautomobile engine control
systems, remote controls,systems, remote controls,
office machines, appliances,office machines, appliances,
power tools, and toyspower tools, and toys
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Microcontroller - AchitectureMicrocontroller - Achitecture
Von-Neuman ArchitecureVon-Neuman Architecure
– single "data" bus that is used to fetch both instructions and datasingle "data" bus that is used to fetch both instructions and data
– pprogram instructions and data are stored in a common mainrogram instructions and data are stored in a common main
memorymemory
– wwhen such a controller addresses main memory, it first fetcheshen such a controller addresses main memory, it first fetches
an instruction, and then it fetches the data to support thean instruction, and then it fetches the data to support the
instruction (if such data is needed).instruction (if such data is needed).
Harvard ArchitectureHarvard Architecture
– separate data bus and an instruction busseparate data bus and an instruction bus
– data and instructions are stored into separate memories that aredata and instructions are stored into separate memories that are
accessed separatelyaccessed separately
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Micocontroller – CISC and RISCMicocontroller – CISC and RISC
Complex Instruction Set Computer (CISC)Complex Instruction Set Computer (CISC)
– a large set of instructions that can perform complex tasksa large set of instructions that can perform complex tasks
– e.g.e.g. the Intel 80X86 series, The Zilog Z80, 8051, 6HC11 etc.the Intel 80X86 series, The Zilog Z80, 8051, 6HC11 etc.
– ffeatures many instructions, addressing modes and takes moreeatures many instructions, addressing modes and takes more
than 1 internal clock cycle to executethan 1 internal clock cycle to execute
Reduced Instruction Set Computer (RISC)Reduced Instruction Set Computer (RISC)
– aa quite small set of instructions which carries out less task perquite small set of instructions which carries out less task per
commandcommand
– complicated operations are carried out by combining manycomplicated operations are carried out by combining many
simple instructionssimple instructions
– eexamples include usage in ARM, SPARC, Atmel AVR MIPS,xamples include usage in ARM, SPARC, Atmel AVR MIPS,
PowerPCPowerPC, PIC, PIC
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PIC microcontrollerPIC microcontroller
Harvard architecture microcontrollers byHarvard architecture microcontrollers by
Microchip TechnologyMicrochip Technology
"Programmable Interface Controller""Programmable Interface Controller" oror
"Programmable Intelligent Computer“"Programmable Intelligent Computer“
Popular due toPopular due to low cost, wide availability, largelow cost, wide availability, large
user base, extensive collection of applicationuser base, extensive collection of application
notes, low cost or free development tools, serialnotes, low cost or free development tools, serial
programmingprogramming,, re-programming with flashre-programming with flash
memory capabilitymemory capability
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Core Architecture ICore Architecture I
separate code and data spaces (Harvard architecture)separate code and data spaces (Harvard architecture)
a small number of fixed length instructionsa small number of fixed length instructions (RISC architecture)(RISC architecture)
most instructions are single cycle execution (4 clock cycles)most instructions are single cycle execution (4 clock cycles)
a single accumulator (W)a single accumulator (W)
a hardware stack for storing return addressesa hardware stack for storing return addresses
a fairly small amount of addressable data space (typically 256a fairly small amount of addressable data space (typically 256
bytes), extended through bankingbytes), extended through banking
data space mapped CPU, portdata space mapped CPU, portss, and peripheral registers, and peripheral registers
the program counter is also mapped into the data space andthe program counter is also mapped into the data space and
writablewritable
no distinction between "memory" and "register" space because theno distinction between "memory" and "register" space because the
RAM serves the job of both memory and registersRAM serves the job of both memory and registers
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Core Architecture IICore Architecture II
Data space – RAMData space – RAM
Code Space - EPROM, ROM, or flashCode Space - EPROM, ROM, or flash
ROMROM
Hardware stackHardware stack
Constant interrupt latencyConstant interrupt latency
35 to 70 intructions, skip intruction,35 to 70 intructions, skip intruction,
conditional execution, branchingconditional execution, branching
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ProgrammingProgramming
Only a single accumulatorOnly a single accumulator
A small instruction setA small instruction set
SSome instructions can address RAM and/or immediate constants,ome instructions can address RAM and/or immediate constants,
while others can only use the accumulatorwhile others can only use the accumulator
DDirect referencirect referencing of ming of meemorymory in arithmetic and logic operationsin arithmetic and logic operations
Register-bank switching is required to access the entireRegister-bank switching is required to access the entire RAMRAM
Conditional skip instructions are used instead of conditional branchConditional skip instructions are used instead of conditional branch
instructionsinstructions
Wide range of device programmers (we will use PIC PRESTO)Wide range of device programmers (we will use PIC PRESTO)
Microchip provides a freeware IDE package called MPLAB, whichMicrochip provides a freeware IDE package called MPLAB, which
includes an assembler, linker, software simulator, and debuggerincludes an assembler, linker, software simulator, and debugger
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Family Core ArchitecturalFamily Core Architectural
DifferencesDifferences
Baseline Core Devices -Baseline Core Devices - PIC10 series, as well as some PIC12 and PIC16 devicesPIC10 series, as well as some PIC12 and PIC16 devices
– 12-bit wide code memory, and a tiny two level deep call stack12-bit wide code memory, and a tiny two level deep call stack
Mid-Range Core Devices - PIC12 and PIC16Mid-Range Core Devices - PIC12 and PIC16
– 14-bit wide code memory, and 8 level deep call stack14-bit wide code memory, and 8 level deep call stack
PIC17 High End Core DevicesPIC17 High End Core Devices – not so popular, supressed by PIC18 architecture– not so popular, supressed by PIC18 architecture
– a memory mapped accumulatora memory mapped accumulator,, read access to code memory (table reads)read access to code memory (table reads),, direct registerdirect register
to register moves (prior cores needed to move registers through the accumulator)to register moves (prior cores needed to move registers through the accumulator)
– an external program memory interface to expand the code spacean external program memory interface to expand the code space
– an 8bit x 8bit hardware multipliean 8bit x 8bit hardware multiplier,r, a second indirect register paira second indirect register pair
PIC18 High End Core DevicesPIC18 High End Core Devices
– much deeper call stack (31 levels deep)much deeper call stack (31 levels deep)
– the call stack may be read and writtenthe call stack may be read and written
– conditional branch instructionsconditional branch instructions
– indexed addressing mode (PLUSW)indexed addressing mode (PLUSW)
– extending the FSR registers to 12 bits, allowing them to linearly address the entire dataextending the FSR registers to 12 bits, allowing them to linearly address the entire data
address spaceaddress space
– the addition of another FSR register (bringing the number up to 3)the addition of another FSR register (bringing the number up to 3)
PIC24 and dsPIC 16-bit MicrocontrollersPIC24 and dsPIC 16-bit Microcontrollers
PIC32MX 32-bit MicrocontrollersPIC32MX 32-bit Microcontrollers
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What do the numbers and prefixWhat do the numbers and prefix
stands for?stands for?
prefix 12 is for chips with 8 pinsprefix 12 is for chips with 8 pins
prefix 16 is for 12-bit and 14-bit core chips with more than 8 pinsprefix 16 is for 12-bit and 14-bit core chips with more than 8 pins
prefix 18 is for 16-bit core chipsprefix 18 is for 16-bit core chips
the letter after number tells the memory type: C is for EPROM (OTPthe letter after number tells the memory type: C is for EPROM (OTP
or windowed (except 16C84 that has EEPROM), F is for flash chipsor windowed (except 16C84 that has EEPROM), F is for flash chips
and JW is for chips that have windowed EPROM (UV erasable)and JW is for chips that have windowed EPROM (UV erasable)
The number (2 or 3 digits) after this letter identifies specific chipThe number (2 or 3 digits) after this letter identifies specific chip
versionversion
Improved new version of certain PIC types are identified byImproved new version of certain PIC types are identified by
appending an A to the type (A chips are in most aspects identical toappending an A to the type (A chips are in most aspects identical to
their non-A predecessors, but there can be some differences usuallytheir non-A predecessors, but there can be some differences usually
on chip programming)on chip programming)