User's Guide EL -12864A. LCM (Liquid Crystal Display Module) -For product support, contact www.ElatecEurope.com support (5)elateceurope.com © 1998 Elatec EL-12864A LCM Use's Guide Contents Chapter 1. Introduction to EL-12864A LCM 1 Features 1 Mechanical Specifications 1 Temperature Characteristics 1 External Dimensions 2 Application Diagram 3 Electro- Optical characteristics 4 Interface Pin Connections 5 Electrical Absolute Maximum Rating (KSO107B) 6 DC Electrical Characteristics (KSO 107B) 6 Electrical Absolute Maximum Rating (KSO 108B) 7 DC Electrical Characteristics (KSO 108B) 7 Chapter 2. Driver IC (KS0107B) Function Description 8 Introduction 8 AC Characteristics 9 Master Mode 9 Slave Mode 10 Functional Description 11 RC Oscillator 11 Timing Generation Circuit 11 Data Shift & Phase Select Control 12 Chapter 3. Driver IC (KS0108B) Function Description 13 Introduction 13 AC Characteristics 13 Operating Principles & Methods 16 Display Control Instruction 19 Chapter 1 Introduction to EL-12864A LCM 1 CHAPTER 1 Introduction to EL-12864A LCM EL-12864A is a dot matrix graphic LCD module which is fabricated by low power COMS technology. It can display 128*64 dots size LCD panel using a 128*64 bit-mapped Display Data RAM (DDRAM). It interfaces with an 8-bit microprocessor. Features Display format: 128*64 dots matrix graphic STN yellow-green mode Easy interface with 8-bit MPU Low power consumption LED back-light Viewing angle: 6 O'clock Driving method : 1/64 duty , 1/6.7 bias LCD driver IC: KS0108B(2 ) KS0107B Connector: Zebra Mechanical Specifications Item Dimension Unit Module Size(W*H*T) 93.0*70.0*10.0 mm Viewing Area(W*H) 72.0*40.0 mm Number of Dots 128.0*64.0 PCS Dot Size(W*H) 0.48*0.48 mm Dot Pitch(W*H) 0.52*0.52 mm Module Size With B/L 93.0*70.0*15.0 mm Temperature Characteristics Parameter Symbol Rating Unit Operating temperature Topr 0-+50 Storage temperature Tstg -20 ~ +70 Chapter 1 Introduction to EL-12864A LCM 2 Figure 1. External Dimensions -93.00--88,00--80,00--72.0--66,52- L 20, 'nnnnnnnnnnnnnnnnnfinrk1 -19XP2,54=48,26- © X02.5 MAX 15,0-9,8±0,3- -H--1.6+0,2 ^cb dJ cb cb mO rÖ^I- cd 0x01,0 1 UV M4 PIN 1 2 3 4 5 6 7 8 9 10 SIGNAL Vss VDD VO D/I R/W E DB0 DB1 DB2 DB3 PIN 11 12 13 14 15 16 17 18 19 20 SIGNAL DB4 DB5 DB6 DB7 CS1 CS2 RES VEE A K *NOTE: 1.A11 units are mm. _2.Tolerances unless otherwise specified ±0.2 ELATEC LCD MODULE EL-12864A Chapter 1 Introduction to EL-12864A LCM 3 Figure 2. Application Diagram LCD panel COM1 (128X64) COM64 SEG1 ■■ ■ ■ SEG64 SEG65 ■ ■ ■ SEG128 Rf Cf IC2 SWS64 KS0108B (Bottom view) < CO CO M FRM CLK1 CLK2 CL2 < > D D D O Z) E Q. RW RS DB[0:7] RESETB CS2 CS1 m vss vss MA S1 TT KS0108B (Bottom view) IC1 < > D D D O M FRM CLK1 CLK2 CL2 C64 C1 R CR C M FRM CLK1 CLK2 CL2 VDD CD SHL O FS O MS PCLK2 OD DS2 DS1 VSS < < < < < < < H o to U fr oi m V1 VEE "Note 1/64 duty, 1/6.7 bias VDD>V 1>V2>V3>V4>V5>VEE Chapter 1 Introduction to EL-12864A LCM 4 Electro-Optical characteristics TN Type (Twisted Nematic) Item Symbol Min. Typ. Max. Unit Condition Note Viewing Angle 92 -Qi 40 deg. Cr = 2.0 1,2 (P Contrast Ratio Cr - 4 - - 9=20° q>= 0° 3 Response Time (rise) tR - 110 - ms 9=20° q>= 0° 4 Response Time (fall) tF - 110 - ms 9=20° q>= 0° 4 STN Type (Super Twisted Nematic ) Item Symbol Min. Typ. Max. Unit Condition Note Viewing Angle 92 -Qi 70 +90 deg. Cr = 2.0 1,2 (P -90 Contrast Ratio Cr - 4 - - 9=20° q>= 0° 3 Response Time (rise) tR - 110 - ms 9=20° q>= 0° 4 Response Time (fall) tF - 110 - ms 9=20° q>= 0° 4 1. Definition of angle JC& |0 2. Definition of viewing angle jCi& |0 2 3. Definition of contrast Cr 4. Definition of optical response P Off Intensity 100% Set Point Driving Voltage Cr = (A/B)p Negative : P =-1 Positive : P = +1 On 100%/ 90% Off 10% Time Chapter 1 Introduction to EL-12864A LCM 5 Interface Pin Connections Pin No. Symbol I/O Type Description 1 vss Supply Ground 2 VDD Supply Power supply 3 vo Supply LCD driver supply voltage 4 D/I Data input/output pin of internal shift register MS SHL DIOl DI02 H H Output Output H L Output Output L H Input Output L L Output Input 5 R/W Read or Write RW Description H Data appears at DB [7:0] and can be read by the CPU while E= H CS1B=L,CS2B=L and CS3=H. L Display data DB [7:0] can be written at falling edge of E when CS1B=L, CS2B=L and CS3=H. 6 E Enable signal E Description H Read data in DB[7:0] appears while E= "High". L Display data DB [7:0] is latched at falling edge of E. 7 DBO I/O Data bus [0-7] 8 9 DBl DB2 Bi-directional data bus 10 DB3 11 DB4 12 DB5 13 DB6 14 DB7 15 CS1 I Chip selection 16 CS2 When CS1=H,CS2=L, select IC1 When CS1=L,CS2=H, select IC2 17 RESETB I Reset signal. When RSTB=L 1 ON/OFF register becomes set by 0.(display off) 2 display start line register becomes set by 0 (Z-address 0 set, display from line 0) 3 After releasing reset, this condition can be changed only by instruction. 18 VEE Power VEE is connected by the same voltage. 19 A Back-light anode 20 K Back-light cathode Chapter 1 Introduction to EL-12864A LCM 6 Electrical Absolute Maximum Ratings (KS0107B) Parameter Symbol Rating Unit Note Operating voltage vDD -0.3-+7.0 V *1 Supply voltage VEE VDD-19.0~VDD+0.3 V *4 Driver supply voltage VB -0.3 ~ VDD+0.3 V *1,2 Vlcd Vee-0.3~Vdd+0.3 V *3,4 *Notes: *1. Based on Vss = 0V *2. Applies to input terminals and I/O terminals at high impedance. (Except VOL, VIL, V4L, and V5L) *3. Applies to VOL, VIL, V4L, and V5L. *4. Voltage level: Vdd>V0>V1>V2>V3>V4>V5>VEe DC Electrical Characteristics(KS0107B) (VDD= 4.5 to 5.5V, VSS=0V,VDD-VEE=8~17V,Ta= -30 to +85 ) Item Symbol Condition Min. Typ. Max. Unit Note Operating voltage vDD - 4.5 5.5 V Input voltage vm - 0.7 vdd - Vdd *1 Vil - Vss - 0.3VDD output voltage Voh I0h= -0.4mA Vdd-0.4 - - *2 Vol I0L= 0.4mA - - 0.4 Input leakage current Ilkg Vin= Vdd ~ Vss -1.0 - +1.0 |iA *1 OSC Frequency fosc Rf=47kQ±2% Cf=20pF±5% 315 450 585 kHz On Resistance Rons VDD-VEE=17V - - 1.5 kQ (Vdiv-Ci) Load current±150|iA Operating current Iddi Master mode 1/128 Duty - - 1.0 mA *3 Idd2 Master mode 1/128 Duty - - 0.2 *4 Supply Current Iee Master mode 1/128 Duty - - 0.1 *5 Operating fopl Master mode External Duty 50 - 600 kHz Frequency fop2 Slave mode 0.5 - 1500 Notes *1. Applies to input terminals FS, DS1, DS2, CR, SHL, MS and PCLK2 and I/O terminals DIOl, DI02, M , and CL2 in the input state. *2. Applies to output terminals CLK1, CLK2 and FRM and I/O terminals DIOl, DI02, M , and CL2 in the output state. *3. This value is specified about current flowing through Vss. Internal oscillation circuit: Rf=47kQ, cf=20pF Each terminals of DS1, DS2, FS, SHL, and MS is connected to Vdd and out is no load. *4. This value is specified about current flowing through Vss. Each terminals is DS1, DS2, FS, SHL, PCLK2 and CR is connected to Vdd.MS is connected to Vss and CL2, M, DIOl is external clock. *5. This value is specified about current flowing through Vee, Don't connect to Vlcd (V1-V5). Chapter 1 Introduction to EL-12864A LCM 7 Electrical Absolute Maximum Ratings(KS0108B) Parameter Symbol Rating Unit Note Operating voltage vDD -0.3-+7.0 V *1 Supply voltage VEE VDD-19.0~VDD+0.3 V *4 Driver supply voltage VB -0.3 ~ VDD+0.3 V *1,3 Vlcd Vee-0.3~Vdd+0.3 V *2 *Notes: *1. Based on Vss = 0V *2. Applies the same supply voltage to Vee. Vlcd=Vdd-Vee. *3. Applies to M, FRM, CLK1,CLK2, CL, RESETB, ADC, CS1B, CS2B,CS3, E, R/W, RS and DB0-DB7. *4. Applies V0L,V2L,V3L and V5L. Voltage level: Vdd>V0>V1>V2>V3>V4>V5>VEe DC Electrical Characteristics(KS0108B) (VDD=4.5to5.5V, VSS =0V,VDD-VEE=8~17V,Ta=-30to+85 ) Item Symbol Condition Min. Typ. Max. Unit Note Operating voltage vDD - 4.5 5.5 V Input High voltage Vihi - 0.7 vdd Vdd *1 ViH2 - 2.0 Vdd *2 Input Low voltage vIL1 - 0 0.3VDD *1 vIL2 - 0 0.8 *2 Output High Voltage Voh I0H= -0.2mA 2.4 - *3 Output Low Voltage Vol I0L= L6mA - 0.4 *3 Input leakage current Ilkg Vin= Vss ~ Vdd -1.0 +1.0 |iA *4 Three-state (OFF) Itsl Vin= Vss ~ Vdd -5.0 5.0 *5 Input Current Driver Input leakage Idil Vin= Vee ~ Vdd -2.0 2.0 *6 current On Resistance Rons Vdd-Vee=15V - 7.5 kQ *8 (Vdiv-Ci) Load current±100|iA Operating current Iddi During Display - 0.1 mA *y Idd2 During Access Access Cycle=lMHz - 0.5 *y Notes * 1. CL, FRM, M, RSTB, CLK1, CLK2 CS1B, CS2B, CS3, E, R/W, RS, DB0-DB7 DB0-DB7 Except DB0-DB7 DB0—DB7 at high impedance V0, VI, V3, V3, V4, V5 1/64 duty , FCLK=250KHZ, Frame Frequency=70HKZ, Output: No Load Vdd-Vee= 15.5V V0L>V2L>= Vdd-2/7(Vdd-Vee)>V3L= Vee+2/7(Vdd-Vee)>V5L 64CH Common Driver For Dot Matrix LCD 8 CHAPTER 2 Driver IC Function Description KS0107 Driver IC 64COM graphic driver for dot matrix LCD Introduction The KS0107B is an :CD driver LSI with 64 channel outputs for dot matrix liquid crystal graphic display systems. This device provides 64 shift registers and 64 output drivers. It generates the timing signal to control the KS0108B (64 channel segment drover.). The KS0107B is fabricated by low power CMOS high voltage process technology, and is composed of the liquid crystal display system in combination with the KS0108B (64 channel segment drover.). © Elatec 64CH Common Driver For Dot Matrix LCD 9 AC Characteristics (VDD=4.5~5.5V, Ta=-30 ~+85 ) 1. Master mode (MS=Vdd, PCLK2=Vdd, Cf=20pF, Rf=47KQ) CL2 DI01(SHL=Vdd) DI02(SHL=Vss^ _ DI02(SHL=Vdd) DIOKSHL=Vss1 FRM M CLK1 CLK2 OJVdd ■ 0.3VDD X J- "tWLC- • tsu -tD- 7 ■ tDM ' tDH tD tsu " tüF tDM HtRh ).7Vdd ).3Vdd \^ ^ twT.l p ' twHl ' -tD 12 -tD21 ■ t\VH2 ■ •tR Characteristic_Symbol Min Typ Max Unit Data Setup Time_tsy_20 _-_ Data Hold Time_toy_40 Data Delay Time_tg_5_-_-_ FRM Delay Time_trjF_-2 - 2 M-s M Delay Time_toM_-2 - 2 CL2 Low Level Width_W_35 CL2 High Level Width_tWHc 35 _ CLK1 Low Level Width_tWLi 700 CLK2 Low Level Width_tWL2 700 CLK1 High Level Width_tWHi 2100 - CLK2 High Level Width_tWH2 2100 - - ns CLK1-CLK2 Phase Difference tD12 700 CLK2-CLK1 Phase Difference tD2i_700 CLK1.CLK2 Rise/Fall Time tR/tF _ 150__ © Elatec 64CH Common Driver For Dot Matrix LCD 10 Slave mode (MS=VSS) CL2 (PLK2=VSS) CL2 (PLK2=VDD) DI01(SHL=VDD) DI02(SHL=VSS) Input Data DI01(SHL=VDD) DI02(SHL=VSS) Output Data tF N -_ tR tR _ / \ tF \_/ .twHci> \ -to- x tH X tsi twLCl , t\VLC2 / \ , t\VLC , •0.7VDD ■0.3Vnn 4-tHCL-► 0.7VDD ■0.3Vnn X 0.3Vnn X Characteristics Symbol Min Typ Max Unit Note CL2 Low Level Width t\VLCl 450 - PCLK2=VSS CL2 High Level Width t\VHCl 150 - PCLK2=VSS CL2 Low Level Width t\VLC2 150 - PCLK2=VDD CL2 High Level Width t\VHL 450 ns PCLK2=Vdd Data Setup Time tsu 100 - Data Hold Time tDH 100 - Data Delay Time to - 200 *1 Output Data Hold Time tH 10 - CL2 Rise/Fall Time tR/tF - 30 *1: Connect load CL=30pF OUTPUT O- "1 /X30pp © Elatec 64CH Common Driver For Dot Matrix LCD 11 FUNCTIONAL DESCRIPTION l.RC Oscillator The RC Oscillator generates CL2, M, FRM, of the KS0107B and CLK1, CLK2 of the KS0107B by the oscillation resister R and capacitor C. When selecting the master/slave, oscillation circuit is as following: 1) Master Mode KS0107B Rf Cf KS0107B R CR C R CR C -AAS— —II— open open External clock 2) Slave Mode KS0107B R open CR V- dd c open 2.Timing Generation circuit It generates CL2, M, FRM, CLK1, and CLK2 by the frequency from oscillation circuit. 1) Selection of Master/Slave (M/S) When M/S is "H", it generates CL2, M, FRM, CLK1, and CLK2 internally. When M/S is "L", it operates by receiving M, CLK2 from master device. 2) Frequency Selection (FS) To adjust FRM by 70Hz, the oscillation frequency should be as following: FS Oscillation Frequency H fosc=430KHz L fOSc=215KHz In the slave mode, it is connected to VDd. © Elatec 64CH Common Driver For Dot Matrix LCD 12 3) Duty Selection (DS1, DS2) It provides various duty selection according to DS1, DS2. DS1 DS2 DUTY L L 1/48 H 1/64 H L 1/96 H 1/128 3. Data shift & Phase Select Control 1) Phase Selection It is a circuit to shift data on synchronization or rising edge or falling edge of the CL2 according to PCLK2. PCLK2 Phase Selection H Data shift on rising edge of CL2 L Data shift on falling edge of CL2 2) Data shift Direction Selection When M/S is connected to VDD, DIOl and DI02 terminal is only output. When M/S is connected to VSS, it depends on the SHL. MS SHL DIOl DI02 Direction of Data H H Output Output C1-C64 L Output Output C64-C1 L H Input Output DI01~C1~C64~DI02 L Output Input DI02~C64~C1~DI01 © Elatec 64CH Segment Driver For Dot Matrix LCD 13 CHAPTER 3 Driver IC Function Description KS0108 Driver IC 64 SEG graphic driver for dot matrix LCD Introduction The KS0108B is an LCD driver LSI with 64 channel outputs for dot matrix liquid crystal graphic display systems. This device consists of the display RAM, 64 bit data latch 64 bit drivers and decoder logics. It has the internal display RAM for storing the display data transferred from a 8 bit micro controller and generates the dot matrix liquid crystal driving signals corresponding to stored data. The KS0108B composed of the liquid crystal display system in combination with the KS0107B(64 common driver). AC Characteristics (VDD=4.5~5.5V ,Vss=0V, Ta=-30 ~+85 ) 1 Clock Timing Characteristic Symbol Min Typ Max Unit CLK1. CLK2 Cycle Time try 2.5 20 us CLKl'LOW'Level Width t\VLl 625 - CLK2'LOW'Level Width t\VL2 625 - CLK1 'HIGH'Level Width t\VHl 1875 - CLK2'HIGH'Level Width t\VH2 1875 ns CLK1-CLK2 Phase Difference tD12 625 - CLK2-CLK1 Phase Difference tü21 625 - CLK1, CLK2 Rise Time tR - 150 CLK1,CLK2 Fall Time tF - 150 © Elatec 64CH Segment Driver For Dot Matrix LCD 14 CLK1 tF —• o.Tv^T 0.3VDD -twLi- ■tcY <-tR -twHl- %_r tD12 CLK2 r, r^^r-"Si tWL2 0.3VDD * tF —I *iD2r <-twH2-► — tF Icy-1 2 .Display Control Timing Characteristic Symbol Min Typ Max Unit FRM Delay Time tnF -2 2 M Delay Time -2 2 us CL 'LOW'Level Width t\VL 35 - CL'HIGH'Level Width t\VH 35 - © Elatec 64CH Segment Driver For Dot Matrix LCD 15 3 . MPU Interface Characteristic_Symbol Min Typ Max Unit E Cycle__1000 E High Level Width twH_450 E Low Level Width_t^_450 _- E Rise Time_t&_-_-_25 E Fall Time_tp_;_;_25 Address Set-Up Time tASu_140 ns Address Hold Time_Uh_10_-_-_ Data Set-Up Time_tgu_200_-_-_ Data Delay Time_to_;_;_320 Data Hold Time (Write) tDHW_10 _- Data Hold Time (Read) tDHR__20__ tc R/W CS1B,CS2B" CS3,RS - DB0-DB7 "twE-► tR- tASU X tASU <-► ^-twH- tAHf F tAH< X < "tDSU- tDHW > MPU Write timing © Elatec 64CH Segment Driver For Dot Matrix LCD 16 tc <-twL-► ?4-twH-►H- -1 - *— ■tR R/W CS1B,CS2B CS3RS DB0-DB7 tASU *■ tASuk- tAH -► tAH -► X X *-tD t\VH < > MPU Read timing OPERATING PRINCIPLES & METHODS 1. I/O Buffer Input buffer controls the status between the enable and disable of chip. Unless the CS1B to CS3 is in active mode, Input or output of data and instruction does not execute. Therefore internal state is not change. But RSTB and ADC can operate regardless CSIB-CS3. 2. Input register Input register is provided to interface with MPU which is different operating frequency. Input register stores the data temporarily before writing it into display RAM. When CS1B to CS3 are in the active mode, R/W and RS select the input register. The data from MPU is written into input register. Then writing it into display RAM. Data latched for falling of the E signal and write automatically into the display data RAM by internal operation. 3. Output register Output register stores the data temporarily from display data RAM when CS1B, CS2B and CS3 are in active mode and R/W and RS=H, stored data in display data RAM is latched in output register. When CS IB to CS3 is in active mode and R/W=H , RS=L, status data (busy check) can read out. To read the contents of display data RAM, twice access of read instruction is needed. In first access, data in display data RAM is latched into output register. In second access, MPU can read data which is latched. That is to read the data in display data RAM, it needs dummy read. But status read is not needed dummy read. © Elatec 64CH Segment Driver For Dot Matrix LCD 17 RS R/W Function L L Instruction H Status read (busy check) H L Data write (from input register to display data RAM ) H Data read (from display data RAM to output register) 4. Reset The system can be initialized by setting RSTB terminal at low level when turning power on, receiving instruction from MPU. When RSTB becomes low, following procedure is occurred. 1. Display off 2. Display start line register become set by 0.(Z-address 0) While RSTB is low, No instruction except status read can by accepted. Therefore, execute other instructions after making sure that DB4= (clear RSTB) and DB7=0 (ready) by status read instruction. The conditions of power supply at initial power up are shown in table 1. Table 1. Power Supply Initial Conditions Item Symbol Min Typ Max Unit Reset Time tRS 1.0 us Rise Time tR - 200 ns 4.5[V^ VDD RSTB ■*-tRS-► «-tR ro.7vDD 0.3VDD 5. Busy flag Busy flag indicates that KS0108B is operating or no operating. When busy flag is high, KS0108B is in internal operating . When busy flag is low, KS0108B can accept the data or instruction. DB7indicates busy flag of the KS0108B. E _I _ ■ ■ Busy Flag_ _ ■ ■ i4—t Busy—►; l/fclk Y-address 0: S1~Y address 63: S64 ADC=L => Y-address 0: S64~Yaddress 63: SI ADC terminal connect the VDd or VSs- 10. Display Start Line Register The display start line register indicates of display data RAM to display top line of liquid crystal display. Bit data (DB<0.5>) of the display start line set instruction is latched in display start line register. Latched data is transferred to the Z address counter while FRM is high, presetting the Z address counter. It is used for scrolling of the liquid crystal display screen. © Elatec 64CH Segment Driver For Dot Matrix LCD 19 Display Control Instruction The display control instructions control the internal state of the KS0108B. Instruction is received from MPU to KS0108B for the display control. The following table shows various instructions. Instruction RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO Function Read Display Date 1 1 Read data Reads data (DB[7:0]> from display data RAM to the data bus. Writes data (DB[7:0]> into Write Display Date 1 0 Write data the DDRAM. After writing instruction, Y address is incriminated by 1 automatically Reads the internal status BUSY 0: Ready Status Read 0 1 Busy 0 ON/ OFF Reset 0 0 0 0 1: In operation ON/OFF 0: Display ON 1: Display OFF RESET 0: Normal 1: Reset Set Address (Y address) 0 0 0 1 Y address (0-63) Sets the Y address at the column address counter Set Display Start Line 0 0 1 1 Display start line (0~63) Indicates the Display Data RAM displayed at the top of the screen. Set Address (X address) 0 0 1 0 1 1 1 Page (0-7) Sets the X address at the X address register. Controls the display ON or OFF. The internal status Display On/off 0 0 0 0 1 1 1 1 1 0/1 and the DDRAM data is not affected. 0: OFF, 1: ON 1. Display On/Off The display data appears when D is 1 and disappears when D is 0. Though the data is not on the screen with D=0, it remains in the display data RAM. Therefore, you can make it appear by changing D=0 into D=l. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 0 0 0 0 1 1 1 1 1 D 2. Set Address (Y Address) Y address (AC0-AC5) of the display data RAM is set in the Y address counter. An address is set by instruction and increased by 1 automatically by read or write operations of display data. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0 © Elatec 64CH Segment Driver For Dot Matrix LCD 20 3. Set Page (X Address) X address (AC0-AC2) of the display data RAM is set in the X address register. Writing or reading to or from MPU is executed in this specified page until the next page is set. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 0 0 1 0 1 1 1 AC2 AC1 ACO 4. Display Start Line (Z Address) Z address (AC0-AC5) of the display data RAM is set in the display start line register and displayed at the top of the screen. When the display duty cycle is 1/64 or others (1/32-1/64), the data of total line number of LCD screen, from the line specified by display start line instruction, is displayed. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 0 0 1 1 AC5 AC4 AC3 AC2 AC1 ACO 5. Status Read RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 1 0 BUSY 0 ON/OFF RESET 0 0 0 0 • BUSY When BUSY is 1, the Chip is executing internal operation and no instructions are accepted. When BUSY is 0, the Chip is ready to accept any instructions. • ON/OFF When ON/OFF is 1, the display is on. When ON/OFF is 0, the display is off. • RESET When RESET is 1, the system is being initialized. In this condition, no instructions except status read can be accepted. When RESET is 0, initializing has finished and the system is in the usual operation condition. 6. Write Display Data Writes data (D0-D7) into the display data RAM. After writing instruction, Y address is increased by 1 automatically. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 0 1 D7 D6 D5 D4 D3 D2 Dl DO 7. Read Display Data Reads data (D0-D7) from the display data RAM. After reading instruction, Y address is increased by 1 automatically. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 1 1 D7 D6 D5 D4 D3 D2 Dl DO © Elatec