Chapter 2
Instructions: Language
of the Computer
Chapter 2 — Instructions: Language of the Computer — 2
Instruction Set
 The repertoire of instructions of a
computer
 Different computers have different
instruction sets
 But with many aspects in common
 Early computers had very simple
instruction sets
 Simplified implementation
 Many modern computers also have simple
instruction sets
§2.1Introduction
Chapter 2 — Instructions: Language of the Computer — 3
The MIPS Instruction Set
 Used as the example throughout the book
 Stanford MIPS commercialized by MIPS
Technologies (www.mips.com)
 Large share of embedded core market
 Applications in consumer electronics, network/storage
equipment, cameras, printers, …
 Typical of many modern ISAs
 See MIPS Reference Data tear-out card, and
Appendixes B and E
Chapter 2 — Instructions: Language of the Computer — 4
Arithmetic Operations
 Add and subtract, three operands
 Two sources and one destination
add a, b, c # a gets b + c
 All arithmetic operations have this form
 Design Principle 1: Simplicity favours
regularity
 Regularity makes implementation simpler
 Simplicity enables higher performance at
lower cost
§2.2OperationsoftheComputerHardware
Chapter 2 — Instructions: Language of the Computer — 5
Arithmetic Example
 C code:
f = (g + h) - (i + j);
 Compiled MIPS code:
add t0, g, h # temp t0 = g + h
add t1, i, j # temp t1 = i + j
sub f, t0, t1 # f = t0 - t1
Chapter 2 — Instructions: Language of the Computer — 6
Register Operands
 Arithmetic instructions use register
operands
 MIPS has a 32 × 32-bit register file
 Use for frequently accessed data
 Numbered 0 to 31
 32-bit data called a “word”
 Assembler names
 $t0, $t1, …, $t9 for temporary values
 $s0, $s1, …, $s7 for saved variables
 Design Principle 2: Smaller is faster
 c.f. main memory: millions of locations
§2.3OperandsoftheComputerHardware
Chapter 2 — Instructions: Language of the Computer — 7
Register Operand Example
 C code:
f = (g + h) - (i + j);
 f, …, j in $s0, …, $s4
 Compiled MIPS code:
add $t0, $s1, $s2
add $t1, $s3, $s4
sub $s0, $t0, $t1
Chapter 2 — Instructions: Language of the Computer — 8
Memory Operands
 Main memory used for composite data
 Arrays, structures, dynamic data
 To apply arithmetic operations
 Load values from memory into registers
 Store result from register to memory
 Memory is byte addressed
 Each address identifies an 8-bit byte
 Words are aligned in memory
 Address must be a multiple of 4
 MIPS is Big Endian
 Most-significant byte at least address of a word
 c.f. Little Endian: least-significant byte at least address
Chapter 2 — Instructions: Language of the Computer — 9
Memory Operand Example 1
 C code:
g = h + A[8];
 g in $s1, h in $s2, base address of A in $s3
 Compiled MIPS code:
 Index 8 requires offset of 32
 4 bytes per word
lw $t0, 32($s3) # load word
add $s1, $s2, $t0
offset base register
Chapter 2 — Instructions: Language of the Computer — 10
Memory Operand Example 2
 C code:
A[12] = h + A[8];
 h in $s2, base address of A in $s3
 Compiled MIPS code:
 Index 8 requires offset of 32
lw $t0, 32($s3) # load word
add $t0, $s2, $t0
sw $t0, 48($s3) # store word
Chapter 2 — Instructions: Language of the Computer — 11
Registers vs. Memory
 Registers are faster to access than
memory
 Operating on memory data requires loads
and stores
 More instructions to be executed
 Compiler must use registers for variables
as much as possible
 Only spill to memory for less frequently used
variables
 Register optimization is important!
Chapter 2 — Instructions: Language of the Computer — 12
Immediate Operands
 Constant data specified in an instruction
addi $s3, $s3, 4
 No subtract immediate instruction
 Just use a negative constant
addi $s2, $s1, -1
 Design Principle 3: Make the common
case fast
 Small constants are common
 Immediate operand avoids a load instruction
Chapter 2 — Instructions: Language of the Computer — 13
The Constant Zero
 MIPS register 0 ($zero) is the constant 0
 Cannot be overwritten
 Useful for common operations
 E.g., move between registers
add $t2, $s1, $zero
Chapter 2 — Instructions: Language of the Computer — 14
Sign Extension
 Representing a number using more bits
 Preserve the numeric value
 In MIPS instruction set
 addi: extend immediate value
 lb, lh: extend loaded byte/halfword
 beq, bne: extend the displacement
 Replicate the sign bit to the left
 c.f. unsigned values: extend with 0s
 Examples: 8-bit to 16-bit
 +2: 0000 0010 => 0000 0000 0000 0010
 –2: 1111 1110 => 1111 1111 1111 1110
Chapter 2 — Instructions: Language of the Computer — 15
Representing Instructions
 Instructions are encoded in binary
 Called machine code
 MIPS instructions
 Encoded as 32-bit instruction words
 Small number of formats encoding operation code
(opcode), register numbers, …
 Regularity!
 Register numbers
 $t0 – $t7 are reg’s 8 – 15
 $t8 – $t9 are reg’s 24 – 25
 $s0 – $s7 are reg’s 16 – 23
§2.5RepresentingInstructionsintheComputer
Chapter 2 — Instructions: Language of the Computer — 16
MIPS R-format Instructions
 Instruction fields
 op: operation code (opcode)
 rs: first source register number
 rt: second source register number
 rd: destination register number
 shamt: shift amount (00000 for now)
 funct: function code (extends opcode)
op rs rt rd shamt funct
6 bits 6 bits5 bits 5 bits 5 bits 5 bits
Chapter 2 — Instructions: Language of the Computer — 17
R-format Example
add $t0, $s1, $s2
special $s1 $s2 $t0 0 add
0 17 18 8 0 32
000000 10001 10010 01000 00000 100000
000000100011001001000000001000002 = 0232402016
op rs rt rd shamt funct
6 bits 6 bits5 bits 5 bits 5 bits 5 bits
Chapter 2 — Instructions: Language of the Computer — 18
MIPS I-format Instructions
 Immediate arithmetic and load/store instructions
 rt: destination or source register number
 Constant: –215 to +215 – 1
 Address: offset added to base address in rs
 Design Principle 4: Good design demands good
compromises
 Different formats complicate decoding, but allow 32-bit
instructions uniformly
 Keep formats as similar as possible
op rs rt constant or address
6 bits 5 bits 5 bits 16 bits
Chapter 2 — Instructions: Language of the Computer — 19
Stored Program Computers
 Instructions represented in
binary, just like data
 Instructions and data stored
in memory
 Programs can operate on
programs
 e.g., compilers, linkers, …
 Binary compatibility allows
compiled programs to work
on different computers
 Standardized ISAs
The BIG Picture
Chapter 2 — Instructions: Language of the Computer — 20
Logical Operations
 Instructions for bitwise manipulation
Operation C Java MIPS
Shift left << << sll
Shift right >> >>> srl
Bitwise AND & & and, andi
Bitwise OR | | or, ori
Bitwise NOT ~ ~ nor
 Useful for extracting and inserting
groups of bits in a word
§2.6LogicalOperations
Chapter 2 — Instructions: Language of the Computer — 21
Shift Operations
 shamt: how many positions to shift
 Shift left logical
 Shift left and fill with 0 bits
 sll by i bits multiplies by 2i
 Shift right logical
 Shift right and fill with 0 bits
 srl by i bits divides by 2i (unsigned only)
op rs rt rd shamt funct
6 bits 6 bits5 bits 5 bits 5 bits 5 bits
Chapter 2 — Instructions: Language of the Computer — 22
AND Operations
 Useful to mask bits in a word
 Select some bits, clear others to 0
and $t0, $t1, $t2
0000 0000 0000 0000 0000 1101 1100 0000
0000 0000 0000 0000 0011 1100 0000 0000
$t2
$t1
0000 0000 0000 0000 0000 1100 0000 0000$t0
Chapter 2 — Instructions: Language of the Computer — 23
OR Operations
 Useful to include bits in a word
 Set some bits to 1, leave others unchanged
or $t0, $t1, $t2
0000 0000 0000 0000 0000 1101 1100 0000
0000 0000 0000 0000 0011 1100 0000 0000
$t2
$t1
0000 0000 0000 0000 0011 1101 1100 0000$t0
Chapter 2 — Instructions: Language of the Computer — 24
NOT Operations
 Useful to invert bits in a word
 Change 0 to 1, and 1 to 0
 MIPS has NOR 3-operand instruction
 a NOR b == NOT ( a OR b )
nor $t0, $t1, $zero
0000 0000 0000 0000 0011 1100 0000 0000$t1
1111 1111 1111 1111 1100 0011 1111 1111$t0
Register 0: always
read as zero
Chapter 2 — Instructions: Language of the Computer — 25
Conditional Operations
 Branch to a labeled instruction if a
condition is true
 Otherwise, continue sequentially
 beq rs, rt, L1
 if (rs == rt) branch to instruction labeled L1;
 bne rs, rt, L1
 if (rs != rt) branch to instruction labeled L1;
 j L1
 unconditional jump to instruction labeled L1
§2.7InstructionsforMakingDecisions
Chapter 2 — Instructions: Language of the Computer — 26
Compiling If Statements
 C code:
if (i==j) f = g+h;
else f = g-h;
 f, g, … in $s0, $s1, …
 Compiled MIPS code:
bne $s3, $s4, Else
add $s0, $s1, $s2
j Exit
Else: sub $s0, $s1, $s2
Exit: …
Assembler calculates addresses
Chapter 2 — Instructions: Language of the Computer — 27
Compiling Loop Statements
 C code:
while (save[i] == k) i += 1;
 i in $s3, k in $s5, address of save in $s6
 Compiled MIPS code:
Loop: sll $t1, $s3, 2
add $t1, $t1, $s6
lw $t0, 0($t1)
bne $t0, $s5, Exit
addi $s3, $s3, 1
j Loop
Exit: …
Chapter 2 — Instructions: Language of the Computer — 28
Basic Blocks
 A basic block is a sequence of instructions
with
 No embedded branches (except at end)
 No branch targets (except at beginning)
 A compiler identifies basic
blocks for optimization
 An advanced processor
can accelerate execution
of basic blocks
Chapter 2 — Instructions: Language of the Computer — 29
More Conditional Operations
 Set result to 1 if a condition is true
 Otherwise, set to 0
 slt rd, rs, rt
 if (rs < rt) rd = 1; else rd = 0;
 slti rt, rs, constant
 if (rs < constant) rt = 1; else rt = 0;
 Use in combination with beq, bne
slt $t0, $s1, $s2 # if ($s1 < $s2)
bne $t0, $zero, L # branch to L
Chapter 2 — Instructions: Language of the Computer — 30
Branch Instruction Design
 Why not blt, bge, etc?
 Hardware for <, ≥, … slower than =, ≠
 Combining with branch involves more work
per instruction, requiring a slower clock
 All instructions penalized!
 beq and bne are the common case
 This is a good design compromise
Chapter 2 — Instructions: Language of the Computer — 31
Signed vs. Unsigned
 Signed comparison: slt, slti
 Unsigned comparison: sltu, sltui
 Example
 $s0 = 1111 1111 1111 1111 1111 1111 1111 1111
 $s1 = 0000 0000 0000 0000 0000 0000 0000 0001
 slt $t0, $s0, $s1 # signed
 –1 < +1  $t0 = 1
 sltu $t0, $s0, $s1 # unsigned
 +4,294,967,295 > +1  $t0 = 0
Chapter 2 — Instructions: Language of the Computer — 32
Procedure Calling
 Steps required
1. Place parameters in registers
2. Transfer control to procedure
3. Acquire storage for procedure
4. Perform procedure’s operations
5. Place result in register for caller
6. Return to place of call
§2.8SupportingProceduresinComputerHardware
Chapter 2 — Instructions: Language of the Computer — 33
Register Usage
 $a0 – $a3: arguments (reg’s 4 – 7)
 $v0, $v1: result values (reg’s 2 and 3)
 $t0 – $t9: temporaries
 Can be overwritten by callee
 $s0 – $s7: saved
 Must be saved/restored by callee
 $gp: global pointer for static data (reg 28)
 $sp: stack pointer (reg 29)
 $fp: frame pointer (reg 30)
 $ra: return address (reg 31)
Chapter 2 — Instructions: Language of the Computer — 34
Procedure Call Instructions
 Procedure call: jump and link
jal ProcedureLabel
 Address of following instruction put in $ra
 Jumps to target address
 Procedure return: jump register
jr $ra
 Copies $ra to program counter
 Can also be used for computed jumps
 e.g., for case/switch statements
Chapter 2 — Instructions: Language of the Computer — 35
Leaf Procedure Example
 C code:
int leaf_example (int g, h, i, j)
{ int f;
f = (g + h) - (i + j);
return f;
}
 Arguments g, …, j in $a0, …, $a3
 f in $s0 (hence, need to save $s0 on stack)
 Result in $v0
Chapter 2 — Instructions: Language of the Computer — 36
Leaf Procedure Example
 MIPS code:
leaf_example:
addi $sp, $sp, -4
sw $s0, 0($sp)
add $t0, $a0, $a1
add $t1, $a2, $a3
sub $s0, $t0, $t1
add $v0, $s0, $zero
lw $s0, 0($sp)
addi $sp, $sp, 4
jr $ra
Save $s0 on stack
Procedure body
Restore $s0
Result
Return
Chapter 2 — Instructions: Language of the Computer — 37
Non-Leaf Procedures
 Procedures that call other procedures
 For nested call, caller needs to save on the
stack:
 Its return address
 Any arguments and temporaries needed after
the call
 Restore from the stack after the call
Chapter 2 — Instructions: Language of the Computer — 38
Non-Leaf Procedure Example
 C code:
int fact (int n)
{
if (n < 1) return 1;
else return n * fact(n - 1);
}
 Argument n in $a0
 Result in $v0
Chapter 2 — Instructions: Language of the Computer — 39
Non-Leaf Procedure Example
 MIPS code:
fact:
addi $sp, $sp, -8 # adjust stack for 2 items
sw $ra, 4($sp) # save return address
sw $a0, 0($sp) # save argument
slti $t0, $a0, 1 # test for n < 1
beq $t0, $zero, L1
addi $v0, $zero, 1 # if so, result is 1
addi $sp, $sp, 8 # pop 2 items from stack
jr $ra # and return
L1: addi $a0, $a0, -1 # else decrement n
jal fact # recursive call
lw $a0, 0($sp) # restore original n
lw $ra, 4($sp) # and return address
addi $sp, $sp, 8 # pop 2 items from stack
mul $v0, $a0, $v0 # multiply to get result
jr $ra # and return
Chapter 2 — Instructions: Language of the Computer — 40
Local Data on the Stack
 Local data allocated by callee
 e.g., C automatic variables
 Procedure frame (activation record)
 Used by some compilers to manage stack storage
Chapter 2 — Instructions: Language of the Computer — 41
Memory Layout
 Text: program code
 Static data: global
variables
 e.g., static variables in C,
constant arrays and strings
 $gp initialized to address
allowing ±offsets into this
segment
 Dynamic data: heap
 E.g., malloc in C, new in
Java
 Stack: automatic storage
Chapter 2 — Instructions: Language of the Computer — 42
Character Data
 Byte-encoded character sets
 ASCII: 128 characters
 95 graphic, 33 control
 Latin-1: 256 characters
 ASCII, +96 more graphic characters
 Unicode: 32-bit character set
 Used in Java, C++ wide characters, …
 Most of the world’s alphabets, plus symbols
 UTF-8, UTF-16: variable-length encodings
§2.9CommunicatingwithPeople
Chapter 2 — Instructions: Language of the Computer — 43
Byte/Halfword Operations
 Could use bitwise operations
 MIPS byte/halfword load/store
 String processing is a common case
lb rt, offset(rs) lh rt, offset(rs)
 Sign extend to 32 bits in rt
lbu rt, offset(rs) lhu rt, offset(rs)
 Zero extend to 32 bits in rt
sb rt, offset(rs) sh rt, offset(rs)
 Store just rightmost byte/halfword
Chapter 2 — Instructions: Language of the Computer — 44
String Copy Example
 C code (naïve):
 Null-terminated string
void strcpy (char x[], char y[])
{ int i;
i = 0;
while ((x[i]=y[i])!='\0')
i += 1;
}
 Addresses of x, y in $a0, $a1
 i in $s0
Chapter 2 — Instructions: Language of the Computer — 45
String Copy Example
 MIPS code:
strcpy:
addi $sp, $sp, -4 # adjust stack for 1 item
sw $s0, 0($sp) # save $s0
add $s0, $zero, $zero # i = 0
L1: add $t1, $s0, $a1 # addr of y[i] in $t1
lbu $t2, 0($t1) # $t2 = y[i]
add $t3, $s0, $a0 # addr of x[i] in $t3
sb $t2, 0($t3) # x[i] = y[i]
beq $t2, $zero, L2 # exit loop if y[i] == 0
addi $s0, $s0, 1 # i = i + 1
j L1 # next iteration of loop
L2: lw $s0, 0($sp) # restore saved $s0
addi $sp, $sp, 4 # pop 1 item from stack
jr $ra # and return
Chapter 2 — Instructions: Language of the Computer — 46
0000 0000 0011 1101 0000 0000 0000 0000
32-bit Constants
 Most constants are small
 16-bit immediate is sufficient
 For the occasional 32-bit constant
lui rt, constant
 Copies 16-bit constant to left 16 bits of rt
 Clears right 16 bits of rt to 0
lui $s0, 61
0000 0000 0011 1101 0000 1001 0000 0000ori $s0, $s0, 2304
§2.10MIPSAddressingfor32-BitImmediatesandAddresses
Chapter 2 — Instructions: Language of the Computer — 47
Branch Addressing
 Branch instructions specify
 Opcode, two registers, target address
 Most branch targets are near branch
 Forward or backward
op rs rt constant or address
6 bits 5 bits 5 bits 16 bits
 PC-relative addressing
 Target address = PC + offset × 4
 PC already incremented by 4 by this time
Chapter 2 — Instructions: Language of the Computer — 48
Jump Addressing
 Jump (j and jal) targets could be
anywhere in text segment
 Encode full address in instruction
op address
6 bits 26 bits
 (Pseudo)Direct jump addressing
 Target address = PC31…28 : (address × 4)
Chapter 2 — Instructions: Language of the Computer — 49
Target Addressing Example
 Loop code from earlier example
 Assume Loop at location 80000
Loop: sll $t1, $s3, 2 80000 0 0 19 9 4 0
add $t1, $t1, $s6 80004 0 9 22 9 0 32
lw $t0, 0($t1) 80008 35 9 8 0
bne $t0, $s5, Exit 80012 5 8 21 2
addi $s3, $s3, 1 80016 8 19 19 1
j Loop 80020 2 20000
Exit: … 80024
Chapter 2 — Instructions: Language of the Computer — 50
Branching Far Away
 If branch target is too far to encode with
16-bit offset, assembler rewrites the code
 Example
beq $s0,$s1, L1
↓
bne $s0,$s1, L2
j L1
L2: …
Chapter 2 — Instructions: Language of the Computer — 51
Addressing Mode Summary
Chapter 2 — Instructions: Language of the Computer — 52
Synchronization
 Two processors sharing an area of memory
 P1 writes, then P2 reads
 Data race if P1 and P2 don’t synchronize
 Result depends on order of accesses
 Hardware support required
 Atomic read/write memory operation
 No other access to the location allowed between the
read and write
 Could be a single instruction
 E.g., atomic swap of register ↔ memory
 Or an atomic pair of instructions
§2.11ParallelismandInstructions:Synchronization
Chapter 2 — Instructions: Language of the Computer — 53
Synchronization in MIPS
 Load linked: ll rt, offset(rs)
 Store conditional: sc rt, offset(rs)
 Succeeds if location not changed since the ll
 Returns 1 in rt
 Fails if location is changed
 Returns 0 in rt
 Example: atomic swap (to test/set lock variable)
try: add $t0,$zero,$s4 ;copy exchange value
ll $t1,0($s1) ;load linked
sc $t0,0($s1) ;store conditional
beq $t0,$zero,try ;branch store fails
add $s4,$zero,$t1 ;put load value in $s4
Chapter 2 — Instructions: Language of the Computer — 54
Translation and Startup
Many compilers produce
object modules directly
Static linking
§2.12TranslatingandStartingaProgram
Chapter 2 — Instructions: Language of the Computer — 55
Assembler Pseudoinstructions
 Most assembler instructions represent
machine instructions one-to-one
 Pseudoinstructions: figments of the
assembler’s imagination
move $t0, $t1 → add $t0, $zero, $t1
blt $t0, $t1, L → slt $at, $t0, $t1
bne $at, $zero, L
 $at (register 1): assembler temporary
Chapter 2 — Instructions: Language of the Computer — 56
Producing an Object Module
 Assembler (or compiler) translates program into
machine instructions
 Provides information for building a complete
program from the pieces
 Header: described contents of object module
 Text segment: translated instructions
 Static data segment: data allocated for the life of the
program
 Relocation info: for contents that depend on absolute
location of loaded program
 Symbol table: global definitions and external refs
 Debug info: for associating with source code
Chapter 2 — Instructions: Language of the Computer — 57
Linking Object Modules
 Produces an executable image
1. Merges segments
2. Resolve labels (determine their addresses)
3. Patch location-dependent and external refs
 Could leave location dependencies for
fixing by a relocating loader
 But with virtual memory, no need to do this
 Program can be loaded into absolute location
in virtual memory space
Chapter 2 — Instructions: Language of the Computer — 58
Loading a Program
 Load from image file on disk into memory
1. Read header to determine segment sizes
2. Create virtual address space
3. Copy text and initialized data into memory
 Or set page table entries so they can be faulted in
4. Set up arguments on stack
5. Initialize registers (including $sp, $fp, $gp)
6. Jump to startup routine
 Copies arguments to $a0, … and calls main
 When main returns, do exit syscall
Chapter 2 — Instructions: Language of the Computer — 59
Dynamic Linking
 Only link/load library procedure when it is
called
 Requires procedure code to be relocatable
 Avoids image bloat caused by static linking of
all (transitively) referenced libraries
 Automatically picks up new library versions
Chapter 2 — Instructions: Language of the Computer — 60
Lazy Linkage
Indirection table
Stub: Loads routine ID,
Jump to linker/loader
Linker/loader code
Dynamically
mapped code
Chapter 2 — Instructions: Language of the Computer — 61
Starting Java Applications
Simple portable
instruction set for
the JVM
Interprets
bytecodes
Compiles
bytecodes of
“hot” methods
into native
code for host
machine
Chapter 2 — Instructions: Language of the Computer — 62
C Sort Example
 Illustrates use of assembly instructions
for a C bubble sort function
 Swap procedure (leaf)
void swap(int v[], int k)
{
int temp;
temp = v[k];
v[k] = v[k+1];
v[k+1] = temp;
}
 v in $a0, k in $a1, temp in $t0
§2.13ACSortExampletoPutItAllTogether
Chapter 2 — Instructions: Language of the Computer — 63
The Procedure Swap
swap: sll $t1, $a1, 2 # $t1 = k * 4
add $t1, $a0, $t1 # $t1 = v+(k*4)
# (address of v[k])
lw $t0, 0($t1) # $t0 (temp) = v[k]
lw $t2, 4($t1) # $t2 = v[k+1]
sw $t2, 0($t1) # v[k] = $t2 (v[k+1])
sw $t0, 4($t1) # v[k+1] = $t0 (temp)
jr $ra # return to calling routine
Chapter 2 — Instructions: Language of the Computer — 64
The Sort Procedure in C
 Non-leaf (calls swap)
void sort (int v[], int n)
{
int i, j;
for (i = 0; i < n; i += 1) {
for (j = i – 1;
j >= 0 && v[j] > v[j + 1];
j -= 1) {
swap(v,j);
}
}
}
 v in $a0, k in $a1, i in $s0, j in $s1
Chapter 2 — Instructions: Language of the Computer — 65
The Procedure Body
move $s2, $a0 # save $a0 into $s2
move $s3, $a1 # save $a1 into $s3
move $s0, $zero # i = 0
for1tst: slt $t0, $s0, $s3 # $t0 = 0 if $s0 ≥ $s3 (i ≥ n)
beq $t0, $zero, exit1 # go to exit1 if $s0 ≥ $s3 (i ≥ n)
addi $s1, $s0, –1 # j = i – 1
for2tst: slti $t0, $s1, 0 # $t0 = 1 if $s1 < 0 (j < 0)
bne $t0, $zero, exit2 # go to exit2 if $s1 < 0 (j < 0)
sll $t1, $s1, 2 # $t1 = j * 4
add $t2, $s2, $t1 # $t2 = v + (j * 4)
lw $t3, 0($t2) # $t3 = v[j]
lw $t4, 4($t2) # $t4 = v[j + 1]
slt $t0, $t4, $t3 # $t0 = 0 if $t4 ≥ $t3
beq $t0, $zero, exit2 # go to exit2 if $t4 ≥ $t3
move $a0, $s2 # 1st param of swap is v (old $a0)
move $a1, $s1 # 2nd param of swap is j
jal swap # call swap procedure
addi $s1, $s1, –1 # j –= 1
j for2tst # jump to test of inner loop
exit2: addi $s0, $s0, 1 # i += 1
j for1tst # jump to test of outer loop
Pass
params
& call
Move
params
Inner loop
Outer loop
Inner loop
Outer loop
Chapter 2 — Instructions: Language of the Computer — 66
sort: addi $sp,$sp, –20 # make room on stack for 5 registers
sw $ra, 16($sp) # save $ra on stack
sw $s3,12($sp) # save $s3 on stack
sw $s2, 8($sp) # save $s2 on stack
sw $s1, 4($sp) # save $s1 on stack
sw $s0, 0($sp) # save $s0 on stack
… # procedure body
…
exit1: lw $s0, 0($sp) # restore $s0 from stack
lw $s1, 4($sp) # restore $s1 from stack
lw $s2, 8($sp) # restore $s2 from stack
lw $s3,12($sp) # restore $s3 from stack
lw $ra,16($sp) # restore $ra from stack
addi $sp,$sp, 20 # restore stack pointer
jr $ra # return to calling routine
The Full Procedure
Chapter 2 — Instructions: Language of the Computer — 67
Effect of Compiler Optimization
0
0.5
1
1.5
2
2.5
3
none O1 O2 O3
Relative Performance
0
20000
40000
60000
80000
100000
120000
140000
160000
180000
none O1 O2 O3
Clock Cycles
0
20000
40000
60000
80000
100000
120000
140000
none O1 O2 O3
Instruction count
0
0.5
1
1.5
2
none O1 O2 O3
CPI
Compiled with gcc for Pentium 4 under Linux
Chapter 2 — Instructions: Language of the Computer — 68
Effect of Language and Algorithm
0
0.5
1
1.5
2
2.5
3
C/none C/O1 C/O2 C/O3 Java/int Java/JIT
Bubblesort Relative Performance
0
0.5
1
1.5
2
2.5
C/none C/O1 C/O2 C/O3 Java/int Java/JIT
Quicksort Relative Performance
0
500
1000
1500
2000
2500
3000
C/none C/O1 C/O2 C/O3 Java/int Java/JIT
Quicksort vs. Bubblesort Speedup
Chapter 2 — Instructions: Language of the Computer — 69
Lessons Learnt
 Instruction count and CPI are not good
performance indicators in isolation
 Compiler optimizations are sensitive to the
algorithm
 Java/JIT compiled code is significantly
faster than JVM interpreted
 Comparable to optimized C in some cases
 Nothing can fix a dumb algorithm!
Chapter 2 — Instructions: Language of the Computer — 70
Arrays vs. Pointers
 Array indexing involves
 Multiplying index by element size
 Adding to array base address
 Pointers correspond directly to memory
addresses
 Can avoid indexing complexity
§2.14ArraysversusPointers
Chapter 2 — Instructions: Language of the Computer — 71
Example: Clearing and Array
clear1(int array[], int size) {
int i;
for (i = 0; i < size; i += 1)
array[i] = 0;
}
clear2(int *array, int size) {
int *p;
for (p = &array[0]; p < &array[size];
p = p + 1)
*p = 0;
}
move $t0,$zero # i = 0
loop1: sll $t1,$t0,2 # $t1 = i * 4
add $t2,$a0,$t1 # $t2 =
# &array[i]
sw $zero, 0($t2) # array[i] = 0
addi $t0,$t0,1 # i = i + 1
slt $t3,$t0,$a1 # $t3 =
# (i < size)
bne $t3,$zero,loop1 # if (…)
# goto loop1
move $t0,$a0 # p = & array[0]
sll $t1,$a1,2 # $t1 = size * 4
add $t2,$a0,$t1 # $t2 =
# &array[size]
loop2: sw $zero,0($t0) # Memory[p] = 0
addi $t0,$t0,4 # p = p + 4
slt $t3,$t0,$t2 # $t3 =
#(p<&array[size])
bne $t3,$zero,loop2 # if (…)
# goto loop2
Chapter 2 — Instructions: Language of the Computer — 72
Comparison of Array vs. Ptr
 Multiply “strength reduced” to shift
 Array version requires shift to be inside
loop
 Part of index calculation for incremented i
 c.f. incrementing pointer
 Compiler can achieve same effect as
manual use of pointers
 Induction variable elimination
 Better to make program clearer and safer
Chapter 2 — Instructions: Language of the Computer — 73
ARM & MIPS Similarities
 ARM: the most popular embedded core
 Similar basic set of instructions to MIPS
§2.16RealStuff:ARMInstructions
ARM MIPS
Date announced 1985 1985
Instruction size 32 bits 32 bits
Address space 32-bit flat 32-bit flat
Data alignment Aligned Aligned
Data addressing modes 9 3
Registers 15 × 32-bit 31 × 32-bit
Input/output Memory
mapped
Memory
mapped
Chapter 2 — Instructions: Language of the Computer — 74
Compare and Branch in ARM
 Uses condition codes for result of an
arithmetic/logical instruction
 Negative, zero, carry, overflow
 Compare instructions to set condition codes
without keeping the result
 Each instruction can be conditional
 Top 4 bits of instruction word: condition value
 Can avoid branches over single instructions
Chapter 2 — Instructions: Language of the Computer — 75
Instruction Encoding
Chapter 2 — Instructions: Language of the Computer — 76
The Intel x86 ISA
 Evolution with backward compatibility
 8080 (1974): 8-bit microprocessor
 Accumulator, plus 3 index-register pairs
 8086 (1978): 16-bit extension to 8080
 Complex instruction set (CISC)
 8087 (1980): floating-point coprocessor
 Adds FP instructions and register stack
 80286 (1982): 24-bit addresses, MMU
 Segmented memory mapping and protection
 80386 (1985): 32-bit extension (now IA-32)
 Additional addressing modes and operations
 Paged memory mapping as well as segments
§2.17RealStuff:x86Instructions
Chapter 2 — Instructions: Language of the Computer — 77
The Intel x86 ISA
 Further evolution…
 i486 (1989): pipelined, on-chip caches and FPU
 Compatible competitors: AMD, Cyrix, …
 Pentium (1993): superscalar, 64-bit datapath
 Later versions added MMX (Multi-Media eXtension)
instructions
 The infamous FDIV bug
 Pentium Pro (1995), Pentium II (1997)
 New microarchitecture (see Colwell, The Pentium Chronicles)
 Pentium III (1999)
 Added SSE (Streaming SIMD Extensions) and associated
registers
 Pentium 4 (2001)
 New microarchitecture
 Added SSE2 instructions
Chapter 2 — Instructions: Language of the Computer — 78
The Intel x86 ISA
 And further…
 AMD64 (2003): extended architecture to 64 bits
 EM64T – Extended Memory 64 Technology (2004)
 AMD64 adopted by Intel (with refinements)
 Added SSE3 instructions
 Intel Core (2006)
 Added SSE4 instructions, virtual machine support
 AMD64 (announced 2007): SSE5 instructions
 Intel declined to follow, instead…
 Advanced Vector Extension (announced 2008)
 Longer SSE registers, more instructions
 If Intel didn’t extend with compatibility, its
competitors would!
 Technical elegance ≠ market success
Chapter 2 — Instructions: Language of the Computer — 79
Basic x86 Registers
Chapter 2 — Instructions: Language of the Computer — 80
Basic x86 Addressing Modes
 Two operands per instruction
Source/dest operand Second source operand
Register Register
Register Immediate
Register Memory
Memory Register
Memory Immediate
 Memory addressing modes
 Address in register
 Address = Rbase + displacement
 Address = Rbase + 2scale × Rindex (scale = 0, 1, 2, or 3)
 Address = Rbase + 2scale × Rindex + displacement
Chapter 2 — Instructions: Language of the Computer — 81
x86 Instruction Encoding
 Variable length
encoding
 Postfix bytes specify
addressing mode
 Prefix bytes modify
operation
 Operand length,
repetition, locking, …
Chapter 2 — Instructions: Language of the Computer — 82
Implementing IA-32
 Complex instruction set makes
implementation difficult
 Hardware translates instructions to simpler
microoperations
 Simple instructions: 1–1
 Complex instructions: 1–many
 Microengine similar to RISC
 Market share makes this economically viable
 Comparable performance to RISC
 Compilers avoid complex instructions
Chapter 2 — Instructions: Language of the Computer — 83
Fallacies
 Powerful instruction  higher performance
 Fewer instructions required
 But complex instructions are hard to implement
 May slow down all instructions, including simple ones
 Compilers are good at making fast code from simple
instructions
 Use assembly code for high performance
 But modern compilers are better at dealing with
modern processors
 More lines of code  more errors and less
productivity
§2.18FallaciesandPitfalls
Chapter 2 — Instructions: Language of the Computer — 84
Fallacies
 Backward compatibility  instruction set
doesn’t change
 But they do accrete more instructions
x86 instruction set
Chapter 2 — Instructions: Language of the Computer — 85
Pitfalls
 Sequential words are not at sequential
addresses
 Increment by 4, not by 1!
 Keeping a pointer to an automatic variable
after procedure returns
 e.g., passing pointer back via an argument
 Pointer becomes invalid when stack popped
Chapter 2 — Instructions: Language of the Computer — 86
Concluding Remarks
 Design principles
1. Simplicity favors regularity
2. Smaller is faster
3. Make the common case fast
4. Good design demands good compromises
 Layers of software/hardware
 Compiler, assembler, hardware
 MIPS: typical of RISC ISAs
 c.f. x86
§2.19ConcludingRemarks
Chapter 2 — Instructions: Language of the Computer — 87
Concluding Remarks
 Measure MIPS instruction executions in
benchmark programs
 Consider making the common case fast
 Consider compromises
Instruction class MIPS examples SPEC2006 Int SPEC2006 FP
Arithmetic add, sub, addi 16% 48%
Data transfer lw, sw, lb, lbu,
lh, lhu, sb, lui
35% 36%
Logical and, or, nor, andi,
ori, sll, srl
12% 4%
Cond. Branch beq, bne, slt,
slti, sltiu
34% 8%
Jump j, jr, jal 2% 0%
Chapter 1 — Computer Abstractions and Technology — 88
Exercises
 Answer the following exercises, and send your
answers as a PDF attachment to the email address
listed below
xamiri@fi.muni.cz
 Leave body of the email blank
 Deadline is March 17th
Chapter 1 — Computer Abstractions and Technology — 89
Exercise 1
 Assume that the stack and the static data segments are empty and
that the stack and global pointers start at address 0x7fff fffc and
0x1000 8000, respectively.
int my_global = 100;
main()
{
int x = 10;
int y = 20;
int z;
z = my_function(x, my_global)
}
int my_function(int x, int y)
{
return x – y;
}
 1) Show the contents of the stack and the static data segments after
each function call.
 2) Write MIPS code for the code above.
Chapter 1 — Computer Abstractions and Technology — 90
Exercise 2
 For the following problems, use the hexadecimal data in the table
below.
 1) If the PC is at address 0x00000000, how many branch (no jump
instructions) do you need to get to the addresses in the table above?
 2) If the PC is at address 0x00000000, how many jump instructions
(no jump register instructions or branch instructions) are required to
get to the target addresses in the table above?
a. 0x00001000
b. 0xFFFC0000
Chapter 1 — Computer Abstractions and Technology — 91
Exercise 3
 Each entry in the following table has code and also shows the
contents of various registers. The notation, “($s1)” shows the
contents of a memory location pointed to by register $s1. The
assembly code in the table is executed in the cycle shown on
parallel processors with a shared memory space. Fill out the table
with the value of the registers for each given cycle.
Processor 1 Processor 2 Cycle
Processor 1 MEM
($s1)
Processor 2
$s4 $t1 $t0 $s4 $t1 $t0
0 2 3 4 99 10 20 30
try: add $t0, $0, $s4 1
try: add $t0, $0, $s4 ll $t1, 0($s1) 2
ll $t1, 0($s1) 3
sc $t0, 0($s1) 4
beqz $t0, try sc $t0, 0($s1) 5
add $s4, $0, $t1 beqz $t0, try 6