IP Core Generation Report for lms


Summary

IP core name	lms_pcore
IP core version	v1.00.a
IP core folder	hdl_prj\ipcore\lms_pcore_v1_00_a
Target platform	Generic Xilinx Platform
Target language	VHDL
Model	lms
Model version	1.4
HDL Coder version	3.2
IP core generated on	28-Oct-2013 11:39:58
IP core generated for	LMS

Target Interface Configuration

You chose the following target interface configuration for lms :

Processor/FPGA synchronization mode: Coprocessing - blocking

Target platform interface table:

Port Name	Port Type	Data Type	Target Platform Interfaces	Bit Range / Address / FPGA Pin
x(k)	Inport	sfix16_En15	AXI4-Lite	x"100"
d(k)	Inport	sfix16_En15	AXI4-Lite	x"104"
e(k)	Outport	sfix16_En15	AXI4-Lite	x"108"

Register Address Mapping

The following AXI4-Lite bus accessible registers were generated for this IP core:

Register Name	Address Offset	Description
IPCore_Reset	0x0	write 0x1 to bit 0 to reset IP core
IPCore_Enable	0x4	enabled (by default) when bit 0 is 0x1
IPCore_Strobe	0x8	write 1 to bit 0 after write all input data
IPCore_Ready	0xC	wait until bit 0 is 1 before read output data
x_k__Data	0x100	data register for port x(k)
d_k__Data	0x104	data register for port d(k)
e_k__Data	0x108	data register for port e(k)

The register address mapping is also in the following C header file for you to use when programming the processor:
include\lms_pcore_addr.h
The IP core name is appended to the register names to avoid name conflicts.

IP Core User Guide

Theory of Operation

This IP core is designed to be connected to an embedded processor with an AXI4-Lite bus. The processor acts as bus master, and the IP core acts as slave. By accessing the generated registers via the AXI4-Lite bus, the processor can control the IP core, and read and write data from and to the IP core.

For example, to reset the IP core, write 0x1 to the bit 0 of IPCore_Reset register. To enable or disable the IP core, write 0x1 or 0x0 to the IPCore_Enable register. To access the data ports of the MATLAB/Simulink algorithm, read or write to the associated data registers.



Processor/FPGA Synchronization

In Coprocessing - blocking mode, the IP core (HW) is generated with explicit blocking synchronization, so it causes embedded processor software execution (SW) to wait for the HW to finish. For example, as shown in the diagram below, for each SW sample, the processor first sends input data to the IP core. The processor then starts the IP core processing by writing 0x1 to the IPCore_Strobe register. The processor then polls the IPCore_Ready register to check whether IP Core has finished its processing. Once the processor reads a value of 0x1 from the IPCore_Ready register, the processor then reads the data out from the IP core.



EDK Environment Integration

This IP Core is generated for the Xilinx EDK environment. The following steps are an example showing how to add the IP core into the EDK environment:
1. Copy the IP core folder into the "pcores" folder in your Xilinx Platform Studio (XPS) project. This step adds the IP core into the XPS project user library.
2. In the XPS project, find the IP core in the user library and add the IP core to the design.
3. Connect the S_AXI port of the IP core to the embedded processor's AXI master port.
4. Connect the clock and reset ports of the IP core to the global clock and reset signals.
5. Assign a base address for the IP core.
6. Connect external ports and add FPGA pin assignment constraints.
7. Generate FPGA bitstream and download the bitstream to target device.

IP Core File List

The IP core folder is located at:
hdl_prj\ipcore\lms_pcore_v1_00_a
Following files are generated under this folder:

IP core definition files
data\lms_pcore_v2_1_0.mpd
data\lms_pcore_v2_1_0.pao

IP core report
doc\lms_ip_core_report.html

IP core HDL source files
hdl\vhdl\LMS_pkg.vhd
hdl\vhdl\LMS.vhd
hdl\vhdl\lms_pcore_dut.vhd
hdl\vhdl\lms_pcore_cop.vhd
hdl\vhdl\lms_pcore_axi_lite_module.vhd
hdl\vhdl\lms_pcore_addr_decoder.vhd
hdl\vhdl\lms_pcore_axi_lite.vhd
hdl\vhdl\lms_pcore.vhd

IP core C header file
include\lms_pcore_addr.h