## ‹make›

 1. We have built C programs before by hand. This is OK if they are
    small.
 2. But the compiler is not the fastest program in the world. We
    often want to compile and test our programs after modifying
    them.
 3. If the program is big (it has many C files), it is wasteful to
    compile every one of those every time we want to test.
 4. This is where ‹make› can help us.
 5. We would like to only compile files that have been modified
    since their respective object files were built.
 6. For instance, we have ‹foo.c›, ‹bar.c› and ‹baz.c› and we build
    the program, so we also have ‹foo.o›, ‹bar.o› and ‹baz.o›. We
    edit ‹foo.c› and want to build the program. We only need to
    compile ‹foo.c› and link the object files.
 7. However, consider there is a header file, which is included by
    ‹bar.c› and ‹baz.c›. If we edit this header, both ‹bar.o› and
    ‹baz.o› need to be rebuilt. Do you understand why?
 8. The program ‹make› can deal with exactly those problems. It
    reads a «makefile» -- a script of sorts, in a special language
    -- and only updates files that need to be updated based on this
    makefile.
 9. The makefile can be called anything, and if we have ‹build.mk›,
    we can tell ‹make› to process it like this:
    
        $ make -f build.mk
    
    However,  if the name is ‹makefile› or ‹Makefile›, it is enough
    to say:
    
        $ make
    
    You can try renaming any of the subsequent makefiles that we
    encounter to ‹makefile› (or ‹Makefile›) and run ‹make› without
    ‹-f›.
10. Now you can continue to ‹build.mk›.
    
        $ micro build.mk
