Computer organization and design ffffi. The Hardware/Software Interface ^hr&	
		Chapter 3
		Arithmetic for Computers
Arithmetic for Computers
Operations on integers
. Addition and subtraction . Multiplication and division . Dealing with overflow
Floating-point real numbers
. Representation and operations
Chapter 3 —Arithmetic for Computers —
Integer Addition
Example: 7 + 6
0
(Carries)
. . . (0) 0    (0) 0    (0)  1     (1)  1     (1) 0    (0) 1
Overflow if result out of range
. Adding +ve and -ve operands, no overflow . Adding two +ve operands
. Overflow if result sign is 1
. Adding two -ve operands
Overflow if result sign is 0
M 14
®
Chapter 3 —Arithmetic for Computers
Integer Subtraction
Add negation of second operand Example: 7-6 = 7 + (-6)
+7:0000 0000 ... 0000 0111 =6: 1111 1111 ... 1111 1010 +1: 0000 0000 ... 0000 0001
Overflow if result out of range
■ Subtracting two +ve or two -ve operands, no overflow
■ Subtracting +ve from -ve operand
Overflow if result sign is 0
■ Subtracting -ve from +ve operand
. Overflow if result sign is 1
Chapter 3 —Arithmetic for Computers — 4
Dealing with Overflow
Some languages (e.g., C) ignore overflow
. Use MIPS addu, addui, subu instructions
Other languages (e.g., Ada, Fortran) require raising an exception
. Use MIPS add, addi, sub instructions . On overflow, invoke exception handler
. Save PC in exception program counter (EPC) register
Jump to predefined handler address
mf cO (move from coprocessor reg) instruction can retrieve EPC value, to return after corrective action
Chapter 3 —Arithmetic for Computers — 5
Arithmetic for Multimedia
Graphics and media processing operates on vectors of 8-bit and 16-bit data
. Use 64-bit adder, with partitioned carry chain
Operate on 8x8-bit, 4x16-bit, or 2x32-bit vectors
. SIMD (single-instruction, multiple-data)
Saturating operations
. On overflow, result is largest representable value
. c.f. 2s-complement modulo arithmetic
. E.g., clipping in audio, saturation in video
Chapter 3 —Arithmetic for Computers — 6
Multiplication
Start with long-multiplication approach
rr	lultiplicand
	
	multiplier
X
1000
1001
product
1000 0000 0000 1000 1001000
Length of product is the sum of operand lengths
Multiplicand	
	Shift left
t	64 bits
64-bit ALU
Product	
	Write
Multiplier Shift right
32 bits
64 bits
14
Chapter 3 —Arithmetic for Computers — 7
Multiplication Hardware
Multiplicand	
	Shift left
	64 bits
t	
64-bit ALU
Product	
	Write
64 bits
Multiplier Shift right
32 bits
Initially 0
14
Chapter 3 —Arithmetic for Computers — 8
Optimized Multiplier
Perform steps in parallel: add/shift
Multiplicand	
1	32 bits
32-bit ALU
	Shift right	
Product		"T
	Write	-«-V,
64 bits
One cycle per partial-product addition
. That's ok, if frequency of multiplications is low
14
Chapter 3 —Arithmetic for Computers — 9
Faster Multiplier
Uses multiple adders . Cost/performance tradeoff
Mplier31 • Mcand Mplier30 • Mcand   Mplier29 • Mcand Mplier28 • Mcand Mplier3 • Mcand   Mplier2 • Mcand     Mplierl • Mcand   MplierO • Mcand
Product63 Product62 ■ ■ ■ Product47..16 . . . Productl ProductO
Can be pipelined
. Several multiplication performed in parallel
Chapter 3 — Arithmetic for Computers — 10
MIPS Multiplication
Two 32-bit registers for product
. HI: most-significant 32 bits ■ LO: least-significant 32-bits
Instructions
. mult rs, rt   /   multu rs, rt
. 64-bit product in HI/LO
. mfhi rd   /   mflo rd
Move from HI/LO to rd
Can test HI value to see if product overflows 32 bits
. mul rd, rs, rt
Least-significant 32 bits of product -> rd
Chapter 3 — Arithmetic for Computers — 11
Division
quotient
cflvidend
divisor
remainder
1001
1000)1001010 -1000 10 101 1010 -1000 10
n-bit operands yield n-bit quotient and remainder
Check for 0 divisor Long division approach
. If divisor < dividend bits
1 bit in quotient, subtract
. Otherwise
. 0 bit in quotient, bring down next dividend bit
Restoring division
. Do the subtract, and if remainder goes < 0, add divisor back
Signed division
. Divide using absolute values
. Adjust sign of quotient and remainder as required
14
Chapter 3 — Arithmetic for Computers — 12
Division Hardware
Q   Start J
1. Subtract the Divisor register from the Remainder register and place the result in the Remainder register
Remainder > 0
Remainder < 0
Test Remainder
2a. Shift the Quotient register to the left, setting the new rightmost bit to 1
2b. Restore the original value by adding the Divisor register to the Remainder register and placing the sum in the Remainder register. Also shift the Quotient register to the left, setting the new least significant bit to 0
3. Shift the Divisor register right 1 bit
No: < 33 repetitions
Initially divisor in left half
Divisor			
	Shift right		
	64 bits		
< r			
Quotient Shift left
32 bits
Initially dividend
Yes: 33 repetitions
Í4
Q   Done ^
Chapter 3 — Arithmetic for Computers — 13
Optimized Divider
Divisor	
i	32 bits f
	Shift right
Remainder	Shift left
	Write
64 bits
One cycle per partial-remainder subtraction Looks a lot like a multiplier!
■ Same hardware can be used for both
14
Chapter 3 — Arithmetic for Computers — 14
Faster Division
Can't use parallel hardware as in multiplier
. Subtraction is conditional on sign of remainder
Faster dividers (e.g. SRT devision) generate multiple quotient bits per step
. Still require multiple steps
Chapter 3 — Arithmetic for Computers — 15
MIPS Division
Use HI/LO registers for result
. HI: 32-bit remainder - LO: 32-bit quotient
Instructions
. div rs, rt / divu rs, rt . No overflow or divide-by-0 checking
Software must perform checks if required
. Use mf hi, mf lo to access result
Chapter 3 — Arithmetic for Computers — 16
Floating Point
Representation for non-integral numbers
. Including very small and very large numbers
Like scientific notation
. -2.34 x 1056 . +0.002 x 10"4 . +987.02 x 109
normalized
not normalized
n binary
±1.xxxxxxx2 x 2yyyy
Types float and double in C
14
Chapter 3 — Arithmetic for Computers —
Floating Point Standard
Defined by IEEE Std 754-1985
Developed in response to divergence of representations
. Portability issues for scientific code
Now almost universally adopted Two representations
. Single precision (32-bit) . Double precision (64-bit)
Chapter 3 — Arithmetic for Computers — 18
IEEE Floating-Point Format
single: 8 bits double: 11 bits
single: 23 bits double: 52 bits
Exponent
Fraction
x = (-1 )s x (1 + Fraction) x 2<ExP°nent-Bias>
S: sign bit (0 => non-negative, 1 => negative) Normalize significand: 1.0 < |significand| < 2.0
. Always has a leading pre-binary-point 1 bit, so no need to represent it explicitly (hidden bit)
. Significand is Fraction with the "1." restored
Exponent: excess representation: actual exponent + Bias
. Ensures exponent is unsigned
. Single: Bias = 127; Double: Bias = 1203
Chapter 3 — Arithmetic for Computers — 19
Single-Precision Range
Exponents 00000000 and 11111111 reserved . Smallest value
. Exponent: 00000001 => actual exponent - 1 - 127 = -126
. Fraction: 000...00 => significand = 1.0
. ±1.0 x 2"126 = ±1.2 x 10"38
Largest value
. exponent: 11111110 => actual exponent = 254 - 127 = +127
. Fraction: 111... 11 => significand « 2.0
. ±2.0 x 2+127 = ±3.4 x 10+38
Chapter 3 — Arithmetic for Computers — 20
Double-Precision Range
Exponents 0000... 00 and 1111... 11 reserved Smallest value
. Exponent: 00000000001 => actual exponent = 1 - 1023 = -1022
. Fraction: 000...00 => significand = 1.0
. ±1.0 x 2"1022 « ±2.2 x 10"308
Largest value
. Exponent: 11111111110 => actual exponent = 2046 - 1023 = +1023
. Fraction: 111... 11 => significand « 2.0
. ±2.0 x 2+1023 = ±1.8 x 10+308
Chapter 3 — Arithmetic for Computers — 21
Floating-Point Precision
Relative precision
. all fraction bits are significant . Single: approx 2~23
Equivalent to 23 x log1Q2 * 23 x 0.3 « 6 decimal digits of precision
. Double: approx 2~52
Equivalent to 52 x log1Q2 ~ 52 x 0.3 ~ 16 decimal digits of precision
Chapter 3 — Arithmetic for Computers — 22
Floating-Point Example
Represent -0.75
. -0.75 = (-1)1 x 1.12x2"1
. S = 1
. Fraction = 1000...002 . Exponent = -1 + Bias
Single: -1 + 127 = 126 = 011111102 . Double: -1 + 1023 = 1022 = 011111111102
Single: 1011111101000...00 Double: 1011111111101000...00
Chapter 3 — Arithmetic for Computers — 23
Floating-Point Example
What number is represented by the single-precision float
11000000101000...00 . S = 1
- Fraction = 01000...002
- Fxponent = 100000012 = 129
x = (-1)1 x(1 +012)x2<129-127> = (-1) x 1.25 x 22 = -5.0
Chapter 3 — Arithmetic for Computers — 24
Floating-Point Addition
Consider a 4-digit decimal example
. 9.999 x 101 + 1.610 x 10"1
1. Align decimal points
. Shift number with smaller exponent . 9.999 x 101 +0.016 x 101
2. Add significands
. 9.999 x 101 + 0.016 x 101 = 10.015 x 101
3. Normalize result & check for over/underflow
. 1.0015 x 102
4. Round and renormalize if necessary
. 1.002 x 102
Chapter 3 — Arithmetic for Computers — 25
Floating-Point Addition
Now consider a 4-digit binary example
. 1.0002 x 2"1 + -1.1102 x 2"2 (0.5 + -0.4375)
1. Align binary points
. Shift number with smaller exponent . 1.0002 x 2"1 +-0.1112 x 2"1
2. Add significands
. 1.0002 x 2"1 +-0.1112 x 2"1 = 0.0012 x 2"1
3. Normalize result & check for over/underflow
■ 1.0002 x 2"^ with no over/underflow
4. Round and renormalize if necessary
. 1.0002 x 2^ (no change) = 0.0625
Chapter 3 — Arithmetic for Computers — 26
FP Adder Hardware
Much more complex than integer adder
Doing it in one clock cycle would take too long
. Much longer than integer operations
. Slower clock would penalize all instructions
FP adder usually takes several cycles
. Can be pipelined
Chapter 3 — Arithmetic for Computers — 27
FP Adder Hardware
Sign Exponent
Fraction
Small ALU
Exponent difference
GL_L>
Control
Increment or decrement
Sign Exponent
IF IF
IF IF
		1
		r
	Shift right	
) *		
	1	
-Co o
Big ALU
if v
< ^ 1 )
Shift left or right
Rounding hardware
Sign
Exponent
Fraction
Fraction
Compare exponents
Shift smaller number right
Add
Normalize
Round
Step 1
Step 2
Step 3
Step 4
Chapter 3 — Arithmetic for Computers — 28
Floating-Point Multiplication
Consider a 4-digit decimal example
- 1.110 x 1010 x 9.200 x 10"5
1. Add exponents
. For biased exponents, subtract bias from sum . New exponent = 10 + -5 = 5
2. Multiply significands
- 1.110 x 9.200 = 10.212 => 10.212 x 105
3. Normalize result & check for over/underflow
- 1.0212 x106
4. Round and renormalize if necessary
- 1.021 x 106
5. Determine sign of result from signs of operands
- +1.021 x 106
Chapter 3 — Arithmetic for Computers — 29
Floating-Point Multiplication
Now consider a 4-digit binary example
- 1.0002 x 2"1 x -1.1102 x 2"2 (0.5 x -0.4375)
1. Add exponents
. Unbiased: -1 + -2 = -3
- Biased: (-1 + 127) + (-2 + 127) = -3 + 254 - 127 = -3 + 127
2. Multiply significands
- 1.0002 x 1.1102 = 1.1102 => 1.1102x2"3
3. Normalize result & check for over/underflow
. 1.1102 x 2~3 (no change) with no over/underflow
4. Round and renormalize if necessary
. 1.1102 x 2-3 (no change)
5. Determine sign: +ve x -ve => -ve
- -1.1102 x 2"3 =-0.21875
Chapter 3 — Arithmetic for Computers — 30
FP Arithmetic Hardware
FP multiplier is of similar complexity to FP adder
. But uses a multiplier for significands instead of an adder
FP arithmetic hardware usually does
. Addition, subtraction, multiplication, division, reciprocal, square-root
. FP    integer conversion
Operations usually takes several cycles . Can be pipelined
Chapter 3 — Arithmetic for Computers — 31
FP Instructions in MIPS
FP hardware is coprocessor 1
■ Adjunct processor that extends the ISA
Separate FP registers
. 32 single-precision: $f0, $f1, ... $f31
. Paired for double-precision: $f0/$f1, $f2/$f3, ...
. Release 2 of MIPs ISA supports 32 x 64-bit FP reg's
FP instructions operate only on FP registers
. Programs generally don't do integer ops on FP data, or vice versa
. More registers with minimal code-size impact
FP load and store instructions
. lwd, ldd, swd, sdd
e.g., ldd $f8, 32($sp)
Chapter 3 — Arithmetic for Computers — 32
FP Instructions in MIPS
Single-precision arithmetic
. add.s, sub.s, mul.s, div.s
. e.g., add.s $f0, $f 1, $f6
Double-precision arithmetic
. add.d,sub.d, mul.d, div.d
. e.g., mul.d $f4, $f4, $f6
Single- and double-precision comparison
. c.xx.s, c.xx.d (xx is eq, It, le, ...) ■ Sets or clears FP condition-code bit
. e.g. c.lt.s $f3, $f4
Branch on FP condition code true or false
. belt, bdf
. e.g., belt TargetLabel
Chapter 3 — Arithmetic for Computers — 33
FP Example: °F to °C
C code:
float f2c (float fahr) { return ((5.0/9.0)*(fahr - 32.0));
}
. fahr in $f12, result in $f0, literals in global memory space
Compiled MIPS code:
f2c: lwd    $f16, const5($gp) lwc2   $f18, const9($gp) div.s $f16, $f16, $f18 lwd   $f18, const32($gp) sub.s $f18, $f12, $f18 mul.s $f0,    $f16, $f18 j r $ra
Chapter 3 — Arithmetic for Computers — 34
FP Example: Array Multiplication
X=X+YxZ
. All 32 x 32 matrices, 64-bit double-precision elements
C code:
void mm (double x[][],
double y[][], double z[][]) { int i, j, k;
for (i = 0; i! = 32; i = i + 1) for (j = 0; j! = 32; j = j + 1) for (k = 0; k! = 32; k = k + 1) x[i][j] = x[i][j]
+ y[i][k] * z[k][j];
}
Addresses of x, y, z in $a0, $a1, $a2, and i, j, k in $s0, $s1, $s2
Chapter 3 — Arithmetic for Computers — 35
FP Example: Array Multiplication
MIPS code:
	li	$t1,	32	#	$t1	=	32 (row size/loop end)
	li	$s0,	0	#	i =	0;	initialize 1st for loop
L1 :	li	$s1,	0	#	j =	0;	restart 2nd for loop
L2:	li	$s2,	0	#	k =	0;	restart 3rd for loop
	Sil	$t2,	$S0, 5	#	$t2	—	i * 32 (size of row of x)
	addu	$t2,	$t2, $s1	#	$t2	=	i * size(row) + j
	Sil	$t2,	$t2, 3	#	$t2	=	byte offset of [i][j]
	addu	$t2,	$a0, $t2	#	$t2	=	byte address of x[i][j]
	l.d	$f4,	0($t2)	#	$f4	=	8 bytes of x[i][j]
L3:	Sil	$to.	$s2, 5	#	$to	—	k * 32 (size of row of z)
	addu	$to,	$t0, $s1	#	$to	=	k * size(row) + j
	Sil	$to.	$t0, 3	#	$to	=	byte offset of [k][j]
	addu	$to,	$a2, $t0	#	$to	=	byte address of z[k][j]
	l.d	$f 16,	0($t0)	#	$f16		8 bytes of z[k][j]
Í4
Chapter 3 — Arithmetic for Computers — 36
FP Example: Array Multiplication
Sil	$t0, $s0, 5		# $t0 = i*32 (size of row of y)
addu	$to,	$t0, $s2	# $t0 = i*size(row) + k
Sil	$to,	$t0, 3	# $t0 = byte offset of [i][k]
addu	$to,	$a1, $t0	# $t0 = byte address of y[i][k]
l.d	$f18,	0($t0)	# $f18 = 8 bytes of y[i][k]
mul.d	$f 16,	$f18, $f16	# $f16 = y[i][k] * z[k][j]
add.d	$f4,	$f4, $f16	# f4=x[i][j] + y[i][k]*z[k][j]
addiu	$s2,	$S2, 1	# $k k + 1
bne	$s2,	$t1, L3	# if (k != 32) go to L3
s. d	$f4,	0($t2)	# x[i][j] = $f4
addiu	$s1 ,	$S1, 1	# $j = j + 1
bne	$s1 ,	$t1, L2	# if (j != 32) go to L2
addiu	$s0,	$S0, 1	# $i = i + 1
bne	$s0,	$t1, L1	# if (i != 32) go to L1
14
Chapter 3 — Arithmetic for Computers — 37
Accurate Arithmetic
IEEE Std 754 specifies additional rounding control
■ Extra bits of precision (guard, round, sticky)
■ Choice of rounding modes
. Allows programmer to fine-tune numerical behavior of a computation
Not all FP units implement all options
■ Most programming languages and FP libraries just use defaults
Trade-off between hardware complexity, performance, and market requirements
Chapter 3 — Arithmetic for Computers — 38
Interpretation of Data
The BIG Picture
Bits have no inherent meaning
. Interpretation depends on the instructions applied
Computer representations of numbers
. Finite range and precision
. Need to account for this in programs
Chapter 3 — Arithmetic for Computers — 39
Associativity
Parallel programs may interleave operations in unexpected orders
. Assumptions of associativity may fail
		(x+v)+z	x+(v+z)
X	-1.50E+38	0.00E+00	-1.50E+38
Y	1.50E+38		1.50E+38
z	1.0	1.0	
		1.00E+00	0.00E+00
Need to validate parallel programs under varying degrees of parallelism
Chapter 3 — Arithmetic for Computers —
x86 FP Architecture
Originally based on 8087 FP coprocessor
■ 8 x 80-bit extended-precision registers
■ Used as a push-down stack
. Registers indexed from TOS: ST(0), ST(1), ...
FP values are 32-bit or 64 in memory
. Converted on load/store of memory operand
■ Integer operands can also be converted on load/store
Very difficult to generate and optimize code
■ Result: poor FP performance
Chapter 3 — Arithmetic for Computers —
x86 FP Instructions
Data transfer	Arithmetic	Compare	Transcendental
F LD mem/ST(i)	FIADDP mem/ST(i)	FICOMP	FPATAN
FISTP mem/ST(i)	FISUBRP mem/ST(i)	FIUCOMP	F2XMI
FLDPI	FIMULP mem/ST(i)	FSTSW AX/mem	FCOS
FLD1	FIDIVRP mem/ST(i)		FPTAN
FLDZ	FSQRT		FPREM
	FABS		FPSIN
	FRNDINT		FYL2X
Optional variations
. I: integer operand
. P: pop operand from stack
. R: reverse operand order
. But not all combinations allowed
Chapter 3 — Arithmetic for Computers — 42
Streaming SIMD Extension 2 (SSE2)
Adds 4 x 128-bit registers
- Extended to 8 registers in AMD64/EM64T
Can be used for multiple FP operands
. 2 x 64-bit double precision . 4 x 32-bit double precision . Instructions operate on them simultaneously
Single-Instruction Multiple-Data
Chapter 3 — Arithmetic for Computers — 43
Right Shift and Division
Left shift by / places multiplies an integer by 2'
Right shift divides by 27 . Only for unsigned integers
For signed integers
. Arithmetic right shift: replicate the sign bit . e.g., -5/4
111110112»2 = 111111102 = -2 Rounds toward -°°
. c.f. 111110112 >» 2 = 001111102 = +62
Chapter 3 — Arithmetic for Computers —
Who Cares About FP Accuracy?
Important for scientific code
. But for everyday consumer use?
. "My bank balance is out by 0.00020!" ©
The Intel Pentium FDIV bug
. The market expects accuracy
. See Colwell, The Pentium Chronicles
®
Chapter 3 — Arithmetic for Computers — 45
Concluding Remarks
ISAs support arithmetic
. Signed and unsigned integers
. Floating-point approximation to reals
Bounded range and precision
. Operations can overflow and underflow MIPS ISA
. Core instructions: 54 most frequently used
. 100% of SPECINT, 97% of SPECFP
. Other instructions: less frequent
Chapter 3 — Arithmetic for Computers —