jan.kral@fi.muni.cz
PA221: Timing Analysis, Pipelining and
Register Retiming
1
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D Flip Flop
Week02: Pipelining 2
REGKČ1 KČ2
clk
REG
KČ3
clk
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D Flip Flop
Week02: Pipelining 3
Clock signal requirements:
❑ Minimum period of signal H (THIGH) (Spartan-3: 0.79 ns)
❑ Minimum period of signal L (TLOW) (Spartan-3: 0.79 ns)
❑ Minimum period / maximum frequency (TMIN / FMAX) (Spartan-3: 630 MHz)
❑ Maximum duration of falling and rising edge (TFALL / TRISE)
CLK
TRISETFALL
THIGH TLOW
T
D Q
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D Flip Flop
Week02: Pipelining 4
D Q
Requirements on input data signal:
❑ TSU = setup time (Spartan-3: 0.53 ns)
❑ TH = hold time (Spartan-3: 0 ns)
CLK
TSU TH
D
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D Flip Flop
Week02: Pipelining 5
D Q
Time parameters of output signal
❑ TCKO = Clock to Output (Spartan-3: 0.24 – 0.72 ns)
CLK
Q
TCKO
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D Flip Flop
Week02: Pipelining 6
D Q
clk
arst
TPULSE MINTRR
Requirements on asynchronous reset
❑ TRR = reset recovery time
❑ TPULSE MIN = minimum pulse width (Spartan-3: 0.87 ns)
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Static Timing
Week02: Pipelining 7
Timing Margin
CLK
Data
TLOG + TROUTE
TSU
TCKO
TSKEW + TJITTER
Timing Margin
= SETUP SLACK
Setup slack = Data required time – Data arrival time
Hold slack = Data arrival time – Data required time
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Static Timing
Week02: Pipelining 8
Data
REG KČ
clk
REG
clk
CLK
Data
TSKEW + TJITTER
TCKO TLOG + TROUTE
SETUP
SLACK TSU
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Timing Example
Week02: Pipelining 9
Clock period (FMAX = 630 MHz): TMIN = 1.59 ns
(TLOG + TROUTE)MAX = TMIN – (TCKO + TSU) = 1.59 ns – (0.72 ns + 0.53 ns) = 0.34 ns
Clock period (FMAX = 200 MHz): TMIN = 5 ns
(TLOG + TROUTE)MAX = TMIN – (TCKO + TSU) = 5 ns – (0.72 ns + 0.53 ns) = 3.75 ns
CLK
Data
TSKEW + TJITTER
TCKO TLOG + TROUTE
SETUP
SLACK TSU
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Timing Margin
Week02: Pipelining 10
Setup slack = Data required time – Data arrival time
Setup slack > 0 (positive slack) – systém is correctly placed & routed
Setup slack < 0 (negative slack) = SETUP TIME VIOLATION; system
is not correctly placed & routed, it will (might) work incorrectly at the
required clock frequency
CLK
Data
TLOG + TROUTE
TSU
TCKO
TSKEW + TJITTER
Timing Margin
= SETUP SLACK
HOLD TIME VIOLATION is usually caused by improper design or
design constraints, i.e. violation of basic design rules and
recommendation for FPGA systems.
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Static Timing Analysis (STA)
Week02: Pipelining 11
Checking requirements on timing of D Flip Flops and other blocks of the whole design. In the
case of the maximum working frequency (designer specifies the maximum clock frequency in
.sdc file in Quartus) STA especially verifies SETUP TIME.
To determine maximum working frequency (Fmax), SETUP
TIME SLACK = 0.
Maximum working frequency of FPGA design is determined by
a path with the minimum setup time slack (worst case path).
CLK
Data
TLOG + TROUTE
TSU
TCKO
TSKEW + TJITTER
Timing Margin
= SETUP SLACK
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Increasing Maximum Working Frequency
Week02: Pipelining 12
Pipelining
Split complicated tasks to more simpler tasks which can
be faster.
REG
Comb. 1
REG
Delay 16 ns
FMAX = 62.6 MHz
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Increasing Maximum Working Frequency
Week02: Pipelining 13
Pipelining
Split complicated tasks to more simpler tasks which can
be faster.
REG
Comb
1 REG
Delay 5 ns
REG
Comb
2 REG
Comb
3
Maximum delay 7 ns => FMAX = 143 MHz
(ideal delay 5.3 ns => FMAX = 187 MHz)
Delay 7 ns Delay 6 ns
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Increasing Maximum Working Frequency
Week02: Pipelining 14
Register Retiming (Balancing)
Move part of the large combinational function to a
different stage. Leads to equivalent function.
REG
Comb 1
REG
Delay 12 ns
FMAX = 83 MHz
Comb
2 REG
Delay 2 ns
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Increasing Maximum Working Frequency
Week02: Pipelining 15
Register Retiming (Balancing)
Move part of the large combinational function to a
different stage. Leads to equivalent function.
REG Comb 1 REG
Delay 8 ns
FMAX = 125 MHz
Comb 2 REG
Delay 7 ns
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Metastability
Week02: Pipelining 16
❑ Temporary incorrect (undefined) output of a digital circuit
❑ Can be caused by violating timing requirements
of D Flip Flops
❑ Can be caused by input data signals violating the
specifications (slow rising edge, signal voltage around
input comparator’s reference voltage)
❑ Usually, it is only short impulse
❑ Generally, metastability is dangerous and we try to
avoid it
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Metastability
Week02: Pipelining 17
❑ Leads to random errors without replication possibility
❑ Strongly depends on environment conditions : working
frequency, power supply voltage, processed data signal,
temperature, humidity, …
❑ Only certain hardware pieces can be affected (depends on
the chip fabrication process)
Consequences
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Task Assignment
Week02: Pipelining 18
always @(posedge clk) begin
Y <= A + B + C + D;
end
always @(posedge clk) begin
Y <= M + N;
M <= A + B;
N <= C + D;
end
+
A
M
B
+
C
N
D
+ Y
D Q
Q
_
D Q
Q
_
D Q
Q
_
A
C
+ YD Q
Q
_
B
D
Pipelining – example
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Task Assignment
Week02: Pipelining 19
❑ Explore the provided template
❑ Set clock constrains in .sdc file
❑ Determine the maximum working frequency of the original design
❑ Use pipelining to achieve higher working frequency
❑ Verify that the function is unchanged (RTL viewer)
❑ Determine the maximum working frequency of the pipelined design
❑ Determine the maximum working frequency for adding four 16-bit numbers
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Clock Constrains
Week02: Pipelining 20
Minimum constrains in .sdc file to analyze clock:
# create input clock which is 12MHz
create_clock -name clk -period 4 [get_ports {clk}]
# derive PLL clocks (required if your design instantiates a PLL)
derive_pll_clocks
# derive clock uncertainty
derive_clock_uncertainty
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Maximum Working Frequency
Week02: Pipelining 21
❑ Maximum working frequency is output of
Timing analyzer:
❑ This is the maximum working frequency
for the design as it is currently routed.
❑ Placer & Router runs until they find a
configuration which satisfies the clock
frequency given in .sdc file.
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Maximum Working Frequency
Week02: Pipelining 22
❑ To find the real maximum working frequency, you need to increase the clock frequency
in .sdc file until router fails to find a solution.
❑ Effect of the increasing clock frequency:
Set frequency Final design frequency
(.sdc) (Timing Analyzer)
50 MHz 122 MHz
125 MHz 180 MHz
190 MHz 201 MHz
220 MHz 266 MHz
270 MHz 212 MHz
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Note: Sigasi License
Week02: Pipelining 23
❑ License is available from A415 only.
❑ IP: 192.168.50.2
❑ Port: 27000