jan.kral@fi.muni.cz
PA221: FIR Filter Verification
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jan.kral@fi.muni.cz
FIR Filter
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FMAX = ?
𝑦 𝑛 = 𝑎 0 𝑥 𝑛 + 𝑎 1 𝑥 𝑛 − 1 + ⋯ + 𝑎 𝑁 𝑥 𝑛 − 𝑁 = ෍
𝑖=0
𝑁
𝑎 𝑖 𝑥[𝑛 − 𝑖]
jan.kral@fi.muni.cz
Assignment
FIR filter design and verification
̶ Design a FIR filter according to specification
- use Matlab to generate filter coefficients
- use Vivado IP core wizard to generate FIR filter module
̶ Verify the FIR functionality (automatic testbench)
- read input data from a file and feed them to the filter
- read reference output data from a file and compare it with actual
filter output
- report results of the verification to a log file, including PASS/FAIL
message and total number of errors detected
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jan.kral@fi.muni.cz
FIR Filter Parameters
̶ Entity (IP core) name FIR_50k
̶ Low-pass FIR, Equiripple
̶ Fpass = 50 kHz, Fstop = 200 kHz
̶ Apass = 1dB, Astop = 40 dB
̶ Sampling frequency 6.25 MHz
̶ Clock frequency 50 MHz (=> 8 clock cycles per sample)
̶ Input: 9b, no fractional part (range -256 to +255)
̶ Output: 9b, no fractional part (range -256 to +255)
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Verification: Self-testing testbench
̶ Automatically generates stimuli for the DUT (design under test)
̶ Automatically verifies correctness of the DUT outputs
̶ Generates a LOG file with simulation results
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FIR Filter Parameters
̶ Instantiate the design under test (DUT; FIR_50k)
̶ Create an initial block that reads data from FIR_din.txt file and feeds
the data to DUT. Note that there should be one sample for each 8
clock cycles (50 MHz clock at 6.25 MHz sampling frequency).
̶ Create an initial block that writes data to FIR_dout_act.txt file
whenever FIR output valid signal is asserted. Each sample on a line.
̶ Create an initial block that reads data from FIR_dout_ref.txt file and
verifies data on the DUT output (whenever FIR output valid signal is
asserted). Any discrepancy is reported to both a textual log file and
simulator console as an error.
̶ Correctly finish the simulation (do not run forever).
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FIR_50k_TB.vhd
Initial Block
stimulus generator
FIR_50k.v
Initial block
output checker
LOG file generator
FIR_din.txt FIR_dout_ref.txt
FIR_sim_log.txt
filtin_data
filtin_dv
filtout_data
filtout_dv
Verification
Initial block
record actual
output
FIR_dout_act.txt
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Expected Waveforms
FIR filter
̶ See the analog waveforms in the ModelSim / Questa.
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FIR filter design: filterDesigner
Matlab Filter Design & Analysis Tool
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Matlab: Filter Design
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Matlab: Filter Design
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Matlab: Filter Design
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Matlab: Filter Design
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Matlab: Filter Design
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Matlab: Filter Design
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̶ Export as TXT or CSV file.
̶ Modify the file into the following format:
̶ c0, c1, c2, …
̶ If you have no Matlab, you can find the exported file in
w03_filter_template/sources/matlab/FIR_50k.fcf
jan.kral@fi.muni.cz
Alternative Tools: Filter Design
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̶ pyfda (https://github.com/chipmuenk/pyfda)
̶ T-Filter – online
̶ (http://t-filter.engineerjs.com/)
̶ FIR Filter Designer - online (https://wirelesslibrary.labs.b-
com.com/FIRfilterdesigner/#/)
̶ GNU Octave (https://www.allaboutcircuits.com/technical-articles/design-of-
fir-filters-design-octave-matlab/)
̶ rePhase (https://www.minidsp.com/applications/advanced-tools/rephase-
fir-tool)
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FIR II IP Core
Quartus IP Core Library
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IP Core
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IP Core
Expected file
format:
c0, c1, c2, …
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IP Core
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IP Core
̶ Calculate number of expected DSP blocks:
1) for non-symmetrical coefficients
2) for symmetrical coefficients
̶ Verify the calculation on Implementation Options tab.
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Verilog: Reading Data from a File
integer fid_din;
reg [256:0] line; // buffer for line read from file
initial begin
// open the file
fid_din = $fopen("../../sources/data/FIR_din.txt", "r");
if (fid_din == 0) begin
$display("ERROR: File not found.");
$finish;
end
// check FEOF and try to read a line from the file
while (!$feof(fid_din) && $fgets(line, fid_din) != 0) begin
if ($sscanf(line, "%d", data) != 1) begin
$display("ERROR: Failed to scan number from line.");
$finish;
end
end
$fclose(fid_din);
end
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Verilog: Writing Data to a File
integer fid_dout_act;
initial begin
// open the file for writing
fid_dout_act = $fopen("../../sources/data/FIR_dout_act.txt", "w");
if (fid_dout_act == 0) begin
$display("ERROR: File could not be opened.");
$finish;
end
while (!sim_finished) begin
// check if the data is valid
if (dv) begin
// write the data to file
$fdisplay(fid_dout_act, "%d", data); // internally adds new line
end
#(CLK_PER); // wait for one clock period
end
$fclose(fid_dout_act); // close the file
end
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