PV200, Week 02: Combination logic - Schematic, basic gates1
PV200
Introduction to hardware description languages
Week 02: Combination logic - Schematic, basic gates
Ing. Jiří Čulen, 5.10.2021
PV200, Week 02: Combination logic - Schematic, basic gates2
Agenda
1. New empty project in the Quartus
2. Schematic editor
3. I/O settings
4. Programming the device
5. Half adder
6. Ful adder
7. Adding of two bits number
PV200, Week 02: Combination logic - Schematic, basic gates3
New empty project in the Quartus
̶ File -> New ->New Quartus Prime Project
̶ Select working directory and name of the
project
̶ Define name of the project
̶ Project type – Empty project
̶ Skip add files
1.
2.
3.
PV200, Week 02: Combination logic - Schematic, basic gates4
New empty project in the Quartus
̶ Select device from the
Board DE1-SoC or manually
5CSEMA5F31C6
̶ Skip EDA Tool Settings
̶ Finish
PV200, Week 02: Combination logic - Schematic, basic gates5
New empty project in the Quartus
̶ Assignment -> Device -> Device and Pin Options
̶ Unused Pins -> As input tri-stated
PV200, Week 02: Combination logic - Schematic, basic gates6
Schematic editor
̶ File -> New -> Block Diagram/Schematic File
PV200, Week 02: Combination logic - Schematic, basic gates7
Schematic editor
̶ We will need four basic gates
A Q
0 1
1 0
A B Q
0 0 0
0 1 0
1 0 0
1 1 1
A B Q
0 0 0
0 1 1
1 0 1
1 1 1
A B Q
0 0 0
0 1 1
1 0 1
1 1 0
PV200, Week 02: Combination logic - Schematic, basic gates8
Schematic editor
̶ We will use keys from the
board, which are in negative
logic. We need to invert it
for positive logic.
PV200, Week 02: Combination logic - Schematic, basic gates9
Schematic editor
−Place a symbol not
PV200, Week 02: Combination logic - Schematic, basic gates10
Schematic editor
−Place one input port and one output
port and connect it to the NOT gate.
−The name of the input port will KEY[0],
of the output LED[0].
−Save the schematic file.
PV200, Week 02: Combination logic - Schematic, basic gates11
I/O settings
̶ Assignment of keys from the DE1-SoC manual
PV200, Week 02: Combination logic - Schematic, basic gates12
I/O settings
̶ Assignment of LEDS from the DE1-SoC manual
PV200, Week 02: Combination logic - Schematic, basic gates13
I/O settings
̶ Processing -> Start -> Start Analysis & Elaboration
PV200, Week 02: Combination logic - Schematic, basic gates14
I/O settings
̶ Assignments -> Pin Planner
̶ Set the right parameters for our pins
PV200, Week 02: Combination logic - Schematic, basic gates15
Programming the device
̶ Compile the project
̶ Open the programmer
̶ Check connection to
the DE SoC board
̶ Select 5CSEMA5
̶ Detect your FPGA
PV200, Week 02: Combination logic - Schematic, basic gates16
Programming the device
̶ FPGA 5CSEMA5 is
detected
PV200, Week 02: Combination logic - Schematic, basic gates17
Programming the device
̶ Add file to the
5CSEMA5 device
from the project
PV200, Week 02: Combination logic - Schematic, basic gates18
Programming the device
̶ Delete device 5CSEMA5
PV200, Week 02: Combination logic - Schematic, basic gates19
Programming the device
̶ Select 5CSEMA5F31
̶ Start the programming
̶ Test your application
PV200, Week 02: Combination logic - Schematic, basic gates20
Half adder
̶ Add the next pair of KEY and LED.
̶ For loading new ports to the I/O planner, You need repeat start of
the Analysis & Elaboration
̶ Compile it and test it.
PV200, Week 02: Combination logic - Schematic, basic gates21
Half adder
̶ Create a new schematic file “half_adder”
̶ Use File -> Create/Update -> Create Symbol Files for Current File
A B SUM CARRY
0 0 0 0
1 0 1 0
0 1 1 0
1 1 0 1
PV200, Week 02: Combination logic - Schematic, basic gates22
Half adder
̶ Put the half adder to the top schematic
̶ Compile it, program it, and test it…
PV200, Week 02: Combination logic - Schematic, basic gates23
Full adder
̶ We can build full adder by using of half
adders or by many others way…
̶ Create the new schematic file “full_adder”,
and create symbol files
A B CIN SUM CARRY
0 0 0 0 0
1 0 0 1 0
0 1 0 1 0
1 1 0 0 1
0 0 1 1 0
1 0 1 0 1
0 1 1 0 1
1 1 1 1 1
PV200, Week 02: Combination logic - Schematic, basic gates24
Full adder
̶ Put the half adder to the top schematic
̶ Compile it, program it, and test it…
PV200, Week 02: Combination logic - Schematic, basic gates25
Adding of two bits number
̶ Modify the top schema and test it
PV200, Week 02: Combination logic - Schematic, basic gates26
Thank you for attention
Ing. Jiří Čulen
jiri.culen@mail.muni.cz