jan.kral@fi.muni.cz PA221: Clock Domain Crossing (CDC): Selected Parts 1 jan.kral@fi.muni.cz Clock Domains in FPGAs 2 jan.kral@fi.muni.cz Clock Domain ❑ A group of Flip-Flops (registers) sensitive to the same clock edge (usually rising one) of the same clock signal. ❑ A minimal difference of clock signal propagation delay to individual Flip-Flops is expected (minimal skew); i.e. all the registers flip at exactly same time instant. Week06: CDC 3 REGKČ1 KČ2 clk REG KČ3 clk jan.kral@fi.muni.cz Clock Signal Distribution Week06: CDC 4 ❑ Goal: to minimize difference of clock signal propagation delay to individual Flip-Flops. (to minimize skew) Xilinx Spartan-3 jan.kral@fi.muni.cz Why to use more clock signals? Week06: CDC 5 ❑ In real designs, more clock signals are enforced by system requirements. For example, data acquisitions requires different clock frequency than a standard communication interface. ❑ Formally: Globally asynchronous, locally synchronous sequential systems ADC interface 122.88 MHz DDS, CIC, FIR 250 MHz Ethernet MAC 125 MHz jan.kral@fi.muni.cz Why to use more clock signals? Week06: CDC 6 ❑ High clock frequency is only suitable for critical parts of the design (fast interfaces, fast data processing blocks) because: ❑ Lower clock frequency puts lower requirements on the programmable interconnect → faster Place and Router procedure (relaxed requirements) ❑ Lower clock frequency → lower dynamic power consumption (lower thermal dissipation) jan.kral@fi.muni.cz Problem: Interfacing between clock domains Week06: CDC 7 ❑ There are usually many data and/or control signals that must pass from one clock domain to another. As clock domains are asynchronous to each other, a special care must be taken to avoid metastability and data loss/duplicity. ADC interface 122.88 MHz DDS, CIC, FIR 250 MHz Ethernet MAC 125 MHz ? ? jan.kral@fi.muni.cz Signal Crossing over Clock Domain Boundary 8 jan.kral@fi.muni.cz CDC: Common Mistake Week06: CDC 9 ❑ Data interface between two clock domains having same reference frequency but derived from their own oscillators. ❑ The oscillators may have same nominal frequency, but the actual frequency is always slightly different. ❑ The difference is not stable over time – clock jitter / wander. ❑ When reading data on the receiver side (in FPGA on the example shown) some data words may be duplicated or skipped. ADC interface 125 MHz FPGA Software Defined Radio Oscillator 125 MHz Oscillator 125 MHz 125.00052 MHz 124.99976 MHz jan.kral@fi.muni.cz Possible Effects Week06: CDC 10 clk_A data_A clk_B 0 2 3 4 5 6 7 8 91 0 1 2 3 5 6 7 8 9data_B FclkA > FclkB Skipping some data words jan.kral@fi.muni.cz Possible Effects Week06: CDC 11 clk_A 0 1 2 3 4 5 6 7 8 FclkA < FclkB clk_B 1 2 3 3 4 5 6 70 Duplicity of some data words jan.kral@fi.muni.cz Possible Effects Week06: CDC 12 clk_A 0 1 2 3 4 5 6 7 8data_A FclkA < FclkB clk_B data_B 1 2 3 XX 4 5 6 70 A metastability can occur when setup/hold time is violated. Invalid (random) data read. jan.kral@fi.muni.cz Possible Effects: Incorrect Bus Data Week06: CDC 13 clk_A 0 1 2 3 4 5 6 7 8data_A clk_B data_B 1 2 XX XX XX 5 6 70 jan.kral@fi.muni.cz Solution Week06: CDC 14 ❑ Simple synchronizer – suitable for control signals or slow data ❑ Asynchronous FIFO buffer – with independent clocks at write and read side; suitable for high-speed data transfers Both solutions can deal with data transfer in one direction only; for bidirectional transfer it is necessary to double each structure. ADC interface 122.88 MHz DDS, CIC, FIR 250 MHz FIFO SYNC SYNC jan.kral@fi.muni.cz Solution Week06: CDC 15 ❑ The actual solution depends on: ❑ Single bit or multiple-bit signal ❑ Clock frequency of source and destination domains ❑ Character of the signal (long or short impulse) ❑ Is a transfer required every clock cycle? http://www.fpga4fun.com/CrossClockDomain.html ADC interface 122.88 MHz DDS, CIC, FIR 250 MHz FIFO SYNC SYNC jan.kral@fi.muni.cz Assignment 16 jan.kral@fi.muni.cz src domain (clk_src) - 50 MHz Sinewave generator sig_src[11:0] Template Week06: CDC 17 Clock divider Clock enable generator ~ ce_src dst domain (clk_dst) – 50.184 MHz REGREG REGREG Signaltap jan.kral@fi.muni.cz Assignment ❑ Observe the cross-domain effects in signaltap ❑ Add FIFO on sig_src to achieve a proper domain crossing ❑ Create your own synchronizer for clock enable signal (and signals with similar waveforms) Week06: CDC 18 jan.kral@fi.muni.cz src domain (clk_src) - 50 MHz Sinewave generator sig_src[15:0] Solution Week06: CDC 19 Clock divider Clock enable generator ~ ce_src dst domain (clk_dst) – 50.184 MHz Signaltap Dual-port asynch. FIFO cdc_flag ce_dst sig_dst[15:0] jan.kral@fi.muni.cz cdc_flag In source domain: ❑ Convert the short input pulses to level changes ❑ each impulse will toggle a signal ❑ prolonged signals can cross the clock-domain boundary In destination domain: ❑ Add two D-flops to remove metastability ❑ Edge detector converts the level changes back one-clock-cycle impulses Week06: CDC 20 jan.kral@fi.muni.cz cdc_flag Week06: CDC 21 Recommended port naming: clk_src clk_dst arst_src (optional) arst_dst (optional) flag_src flag_dst jan.kral@fi.muni.cz cdc_flag ❑ You should add timing constraints → timing analyzer should ignore only the path with cdc_flag. ❑ Other paths will be unaffected and still analyzed for timing correctness. Week06: CDC 22