Design of Digital Systems II
Digital Circuits
Moslem Amiri, Vaclav Prenosil
Embedded Systems Laboratory Faculty of Informatics, Masaryk University Brno, Czech Republic
amiriOmail.muni.cz prenosilOfi.muni.cz
October, 2012
Introduction
• Voltages, currents, and other physical quantities in real circuits take on values that are infinitely variable
• Stability and accuracy in physical quantities are difficult to obtain, hence they cannot be used to represent real numbers
• Also, many mathematical and logical operations can be difficult or impossible to perform with analog quantities
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Logic Signals and Gates
• Digital logic hides pitfalls of analog world by mapping infinite set of real values for a physical quantity into two subsets corresponding to two logic values—0 and 1
• A logic value, 0 or 1, is called a binary digit, or bit
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Logic Signals and Gates
Table 1: Physical states representing bits in different logic and memory techs.
	State Representing Bit	
Technology	0	/
Pneumatic logic	Fluid at low pressure	Fluid at high pressure
Relay logic	Circuit open	Circuit closed
Complementary metal-oxide	0-1.5 V	3 .5-5.0 V
semiconductor (CMOS) logic		
Transistor-transistor logic (TTL)	0-0.8 V	2 .0-5.0 V
Dynamic memory	Capacitor discharged	Capacitor charged
Nonvolatile, erasable memory	Electrons trapped	Electrons released
Microprocessor on-chip serial number	Fuse blown	Fuse intact
Polymer memory	Molecule in state A	Molecule in state B
Fiber optics	Light off	Light on
Magnetic disk or tape	Flux direction "north"	Flux direction "soudi"
Compact disc (CD)	No pit	Pit
Wnteable compact disc (CD-R)	Dye in crystalline state	Dye in noncrystalline state
• In Tab. 1, with most phenomena, there is an undefined region between 0 and 1 states, so that 0 and 1 states can be unambiguously defined
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Logic Signals and Gates
• When discussing electronic logic circuits such as CMOS and TTL
• LOW: A signal in the range of lower voltages, which is interpreted as a logic 0
• HIGH: A signal in the range of higher voltages, which is interpreted as a logic 1
• Positive logic
• Assignment of 0 to LOW and 1 to HIGH
• Negative logic
• Assignment of 1 to LOW and 0 to HIGH
• A wide range of physical values represent the same binary value
• Hence, digital logic is immune to component and power-supply variations and noise
• Buffer circuits can also be used to regenerate or amplify weak values into strong ones
• E.g., a buffer for CMOS logic converts any HIGH (LOW) input voltage into an output very close to 5.0 V (0.0 V)
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Logic Signals and Gates
Inputs X — Y — Z —
logic circuit
Output
Figure 1: "Black-box" representation of a 3-input, 1-output logic circuit.
• Black-box representation of a logic circuit does not describe how the circuit responds to input signals
• It takes a lot of information to describe electrical behavior of a circuit
• But, a circuit's logical operation can be described with a table
Moslem Amiri, Václav Přenosi
Design of Digital Systems II
October, 2012
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Logic Signals and Gates
• Combinational circuit
• A logic circuit whose outputs depend only on its current inputs
• Its operation is fully described by a truth table
• Truth table lists all combinations of input values and the output value(s) produced by each one
Table 2: Truth table for a combinational logic circuit with three inputs X, Y, and Z and a single output F.
x	Y	z	F
0	0	0	0
0	0	1	1
0	1	0	0
0	1	1	0
1	0	0	0
1	0	1	0
1	1	0	1
1	1	1	1
Moslem Amiri, Václav Přenosil
Design of Digital Systems II
October, 2012
7/53
Logic Signals and Gates
• Sequential circuit
• A circuit with memory, whose outputs depend on current input and sequence of past inputs
• Its behavior may be described by a state table
• State table specifies its output and next state as functions of its current state and input
Moslem Amiri, Václav Přenosi
Design of Digital Systems II
October, 2012
8/53
Logic Signals and Gates
• Three basic logic functions, AND, OR, and NOT can be used to build any combinational digital logic circuit
(AND v x-y
(b)
:or y
x + y
NOTX
X	y	XAND y	X	y	X OR y	X	NOTX
0	0	0	0	0	0	0	1
0	1	0	0	1	1	1	0
1	0	0	1	0	1		
1	1	1	1	1	1		
Figure 2: Basic logic elements: (a) AND; (b) OR; (c) NOT (inverter).
• The circle on inverter symbol's output is called an inversion bubble
• Used to denote "inverting" behavior
Moslem Amiri, Václav Přenosi
Design of Digital Systems II
October, 2012
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Logic Signals and Gates
• Two more logic functions are obtained by combining inversion with an AND or OR function in a single gate
x
(a) ~
X NAND Y (X-Y)'
X Y X NAND Y
0 0 1
0 1 1
1 0 1 1 1 0
(b)
X NOR Y
(X + Y)'
X Y X NOR Y
0 0 1
0 1 0
1 0 0 1 1 0
Figure 3: Inverting gates: (a) NAND; (b) NOR.
• Symbols and truth tables for AND, OR, NAND, and NOR may be extended to gates with any number of inputs
Moslem Amiri, Václav Přenosil
Design of Digital Systems II
10 / 53
Logic Signals and Gates
>
Figure 4: Logic circuit with the truth table of Tab. 2.
/						I
/						
				1	_l \_	
				\		
	\			\		\
	/	\	1	\	/	
TIME
Figure 5: Timing diagram for the logic circuit shown in Fig. 4.
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Logic Families
• Electronic logic circuit development
• In 1930s, the first electronically controlled logic circuits, developed at Bell Laboratories, were based on relays
• In mid-1940s, the first electronic digital computer, Eniac, used logic circuits based on vacuum tubes
• In late 1950s, semiconductor diode and bipolar junction transistor were invented
• Allowed development of smaller, faster, and more capable computers
• In 1960s, integrated circuit (IC) was invented
• Allowed multiple diodes, transistors, and other components to be fabricated on a single chip
• In 1960s, the first IC logic families were also introduced
• A logic family is a collection of different IC chips that have similar input, output, and internal circuit characteristics, but that perform different logic functions
• Chips from same family can be interconnected
• Chips from different families may not be compatible
Moslem Amiri, Václav Přenosi
Design of Digital Systems II
12 / 53
Logic Families
• Transistor-transistor logic (TTL)
• The most successful bipolar logic family
• Based on bipolar junction transistors
• First introduced in 1960s
• TTL evolved into a family of logic families that were compatible with each other but differed in speed, power consumption, and cost
• Metal-oxide semiconductor field-effect transistor (MOSFET) or simply MOS transistor
• Its principles were introduced ten years before bipolar junction transistor
• Difficult to fabricate in early days until 1960s
• Even in 1960s, MOS circuits were slower than bipolar ones, but attractive in a few applications because of their lower power consumption and higher levels of integration
• Beginning in mid-1980s, advances in design of MOS circuits, in particular complementary MOS (CMOS) circuits, tremendously increased their performance and popularity
• Almost all new SSI, MSI, and LSI ICs use CMOS with equivalent functionality or better than TTL, higher speed and lower power consumption
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CMOS Logic: CMOS Logic Levels
• A typical CMOS logic circuit operates from a 5-volt power supply
• Any voltage in range 0-1.5 V —> logic 0
• Any voltage in range 3.5-5.0 V —> logic 1
• Voltages in intermediate range (1.5-3.5 V) are not expected to occur except during signal transitions
• They yield undefined logic values
• A circuit may interpret them as either 0 or 1
5.0 V 3.5 V
1.5 V 0.0 V
Logic 1 (HIGH)
Logic 0 (LOW)
undefined logic level
Figure 6: Logic levels for typical CMOS logic circuits.
Moslem Amiri, Václav Přenosi
Design of Digital Systems II
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CMOS Logic: MOS Transistors
• A MOS transistor can be modeled as a 3-terminal device that acts like a voltage-controlled resistance
• An input voltage applied to one terminal controls resistance between remaining two terminals
• Off transistor
• Its resistance is very high
• On transistor
• Its resistance is very low
Figure 7: The MOS transistor as a voltage-controlled resistance.
Moslem Amiri, Václav Přenosí
Design of Digital Systems II
October, 2012
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CMOS Logic: MOS Transistors
• Two types of MOS transistors
• n-channel
• p-channel
• n-channel MOS (NMOS) transistor
gate
JVoltage-controlled resistance: drain      increase V   ==> decrease R,
1 source
vgs_      I Note: normally, Vgs >0
Figure 8: Circuit symbol for an n-channel MOS (NMOS) transistor. • In Fig. 8
• Orientation shows that drain is normally at a higher voltage than source
• Vgs — 0 —> Rds is very high
• As we increase V^, Rds decreases to a very low value
Moslem Amiri, Václav Přenosi
Design of Digital Systems II
16 / 53
CMOS Logic: MOS Transistors
• p-channel MOS (PMOS) transistor
source
Voltage-controlled resistance: decrease Vn<! ==> decrease R,
'ds
gate
n
drain
Note: normally, Vgs <0
Figure 9: Circuit symbol for a p-channel MOS (PMOS) transistor. • In Fig. 9
• Orientation shows that source is normally at a higher voltage than drain
• Vgs — 0 —> Rds is very high
• As we decrease V^, Rds decreases to a very low value
Moslem Amiri, Vaclav Přenosi
Design of Digital Systems II
October, 2012
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CMOS Logic: MOS Transistors
• Gate of a MOS transistor
• Gate is capacitively coupled to source and drain
• Power needed to charge and discharge this capacitance on each input-signal transition accounts for a nontrivial portion of a circuit's power consumption
• Gate is separated from source and drain by an insulating material with a very high resistance
• Almost no current flows from gate to source, or from gate to drain
• Small amount of current that flows across this resistance is very small, less than one /iA, and is called a leakage current
• Gate voltage creates an electric field that enhances or retards flow of current between source and drain
• This is "field effect" in "MOSFET" name
Moslem Amiri, Václav Přenosi
Design of Digital Systems II
18 / 53
CMOS Logic: Basic CMOS Inverter Circuit
• NMOS and PMOS transistors are used together in a complementary way to form CMOS logic
• Logic inverter
• The simplest CMOS circuit
• Requires only one of each type of transistor
ynn = +5.ov
(a)
Q2
(p-channel)
(b)		QJ	Q2	^OUT
	0.0 (L)	off	on	5.0 (H)
	5.0 (H)	on	off	0.0 (L)
Ql
(n-channel)
□
(C)
IN
1»
OUT
Figure 10: CMOS inverter: (a) circuit diagram; (b) functional behavior; (c) logic symbol.
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CMOS Logic: Basic CMOS Inverter Circuit
ynn = +5.ov
(b)
^to = l □   I     +-nvOVT = H        v]n = hd-
yDD = +5.ov
4
1
Figure 11: Switch model for CMOS inverter: (a) LOW input; (b) HIGH input.
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CMOS Logic: Basic CMOS Inverter Circuit
• Another way of drawing CMOS circuits is shown in Fig. 12
• Different symbols are used for p- and n-channel transistors to reflect their logical behavior
• Inversion bubble on p-channel indicates its inverting behavior (compared to n-channel)
= +5.0 V
Q2 (p-channel)
Qi
(n-channel)
on when
on when Vin is hi9h
Figure 12: CMOS inverter logical operation.
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CMOS Logic: CMOS NAND and NOR Gates
• A /c-input NAND or NOR gate uses k p-channel and k n-channel
transistors
(a)
A LI-
ES □-
o|     Q2  j-o|
Ql
Q3
Q4
(b)
(c)
A	B	Ql	Q2	Q3	Q4	Z
L	L	off	on	off	on	H
L	H	off	on	on	off	H
H	L	on	off	off	on	H
H	H	on	off	on	off	L
Figure 13: CMOS 2-input NAND gate: (a) circuit diagram; (b) function table; (c) logic symbol.
Moslem Amiri, Václav Přenosi
Design of Digital Systems II
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CMOS Logic: CMOS NAND and NOR Gates
Figure 14: Switch model for CMOS 2-input NAND gate: (a) both inputs LOW; (b) one input HIGH; (c) both inputs HIGH.
Moslem Amiri, Václav Přenosil
Design of Digital Systems II
23 / 53
CMOS Logic: CMOS NAND and NOR Gates
(a)
Figure 15: CMOS 2-input NOR gate: logic symbol.
A	B	Ql	Q2	Q3	Q4	Z
L	L	off	on	off	on	H
L	H	off	on	on	off	L
H	L	on	off	off	on	L
H	H	on	off	on	off	L
a) circuit diagram; (b) function table; (c)
Moslem Amiri, Václav Přenosil
Design of Digital Systems II
24 / 53
CMOS Logic: CMOS NAND and NOR Gates
• NAND vs. NOR
• An n-channel transistor has lower "on" resistance than a p-channel
• When transistors are put in series, k n-channel transistors have lower "on" resistance than do k p-channel ones
• As a result, a /(-input NAND gate is faster than a /(-input NOR gate
Moslem Amiri, Vaclav Přenosi
Design of Digital Systems II
25 / 53
CMOS Logic: Fan-In
• Logic family's fan-in
• Number of inputs that a gate can have in a particular logic family
• An n-input gate has n series and n parallel transistors
(a)
a a
b d
c d
(b)
(c)
a	b	c	QI	Q2	Q3	Q4	QS	Q6	z
L	L	L	off	on	off	on	off	on	H
L	L	H	off	on	off	on	on	off	H
L	H	L	off	on	on	off	off	on	H
L	H	H	off	on	on	off	on	off	H
H	L	L	on	off	off	on	off	on	H
H	L	H	on	off	off	on	on	off	H
H	H	L	on	off	on	off	off	on	H
H	H	H	on	off	on	off	on	off	L
Figure 16: CMOS 3-input NAND gate: (a) circuit diagram; (b) function table; (c) logic symbol.
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CMOS Logic: Fan-In
• Additive "on" resistance of series transistors limits fan-in of CMOS gates, typically to 4 for NOR gates and 6 for NAND gates
• As number of inputs is increased, designers may compensate by increasing the size of series transistors to reduce their resistance and corresponding switching delay
• At some point, this becomes inefficient
• Gates with a large number of inputs can be made faster and smaller by cascading gates with fewer inputs
11 T
i2d 13 d
i4 d
15 d
16 d i7d i8 d
OUT
Figure 17: Logic diagram equivalent to the internal structure of an 8-input CMOS NAND gate; (total delay through a 4-input NAND, a 2-input NOR, an inverter) < (delay of a one-level 8-input NAND).
Moslem Amiri, Václav Přenosi
Design of Digital Systems I
October, 2012
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CMOS Logic: Noninverting Gates
• In CMOS, the simplest gates are inverters, and then NAND and NOR
• Inversion comes for free
• Not possible to design a noninverting gate with a smaller number of transistors than an inverting one
• CMOS noninverting buffer, AND, and OR gates are obtained by connecting an inverter to output of corresponding inverting gate
(a)
A □—I
Z
(b)     A    Ql   Q2   Q3   Q4 Z
L off on on off L H   on   off  off  on H
\    Ql 1—I Q3
(c)
Figure 18: CMOS noninverting buffer: (a) circuit diagram; (b) function table; (c) logic symbol.
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CMOS Logic: Noninverting Gates
(a)
A d
B □-
"DD
o|     Q2 j-o|    Q4 j—o|
Ql
Q6
Q5
(b)
(c)
A	B	Ql	Q2	Q3	Q4	Q5	Q6	Z
L	L	off	on	off	on	on	off	L
L	H	off	on	on	off	on	off	L
H	L	on	off	off	on	on	off	L
H	H	on	off	on	off	off	on	H
Figure 19: CMOS 2-input AND gate: (a) circuit diagram; (b) function table; (c) logic symbol.
Moslem Amiri, Václav Přenosí
Design of Digital Systems II
29 / 53
CMOS Logic: AND-OR-INVERT, OR-AND-INVERT Gates
(a)
A □-
b □-
c □-
d □-
DD
J-
-o|    02 i—o|
Q6
r1
07
í
04
QS
Q3
e;
(b)
A	b	C	d	Ql	Q2	Q3	Q4	QS	06	07	QS	z
L	L	L	L	off	on	off	on	off	on	off	on	h
L	L	L	h	off	on	off	on	off	on	on	off	h
L	L	h	L	off	on	off	on	on	off	off	on	h
L	L	h	h	off	on	off	on	on	off	on	off	L
L	h	L	L	off	on	on	off	off	on	off	on	h
L	h	L	h	off	on	on	off	off	on	on	off	h
L	h	h	L	off	on	on	off	on	off	off	on	h
L	h	h	h	off	on	on	off	on	off	on	off	L
h	L	L	L	on	off	off	on	off	on	off	on	h
h	L	L	h	on	off	off	on	off	on	on	off	h
h	L	h	L	on	off	off	on	on	off	off	on	h
h	L	h	h	on	off	off	on	on	off	on	off	L
h	h	L	L	on	off	on	off	off	on	off	on	L
h	h	L	h	on	off	on	off	off	on	on	off	L
h	h	h	L	on	off	on	off	on	off	off	on	L
h	h	h	h	on	off	on	off	on	off	on	off	L
Figure 20: CMOS AND-OR-INVERT (AOI) gate: (a) circuit diagram; (b) function table.
Moslem Amiri, Václav Prenosí
Design of Digital Systems II
30 / 53
CMOS Logic: AND-OR-INVERT, OR-AND-INVERT Gates
• CMOS circuits can perform two levels of logic with just a single "level" of transistors
• Fig. 20
» A 2-wide, 2-input CMOS AND-OR-INVERT (AOI) gate
• Transistors can be added to or removed from this circuit to obtain an AOI function with a different number of ANDs or inputs per AND
• Q1-Q8 depend only on input signal connected to the corresponding transistor's gate
• Z never connected to both Vqd and ground for any input combination
• Otherwise output would be a nonlogic value somewhere between LOW and HIGH, and output structure would consume excessive power due to low-impedance connection between Vqd and ground
Figure 21: Logic diagram for CMOS AOI gate shown in Fig. 20.
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CMOS Logic: AND-OR-INVERT, OR-AND-INVERT Gates
(a)
(b)
A	B	C	d	Ql	Q2	Q3	Q4	QS	Q6	07	QS	Z
L	L	L	L	off	on	off	on	off	on	off	on	H
L	L	L	H	off	on	off	on	off	on	on	off	H
L	L	H	L	off	on	off	on	on	off	off	on	H
L	L	H	H	off	on	off	on	on	off	on	off	H
L	H	L	L	off	on	on	off	off	on	off	on	H
L	H	L	H	off	on	on	off	off	on	on	off	L
L	H	H	L	off	on	on	off	on	off	off	on	L
L	H	H	H	off	on	on	off	on	off	on	off	L
H	L	L	L	on	off	off	on	off	on	off	on	H
H	L	L	H	on	off	off	on	off	on	on	off	L
H	L	H	L	on	off	off	on	on	off	off	on	L
H	L	H	H	on	off	off	on	on	off	on	off	L
H	H	L	L	on	off	on	off	off	on	off	on	H
H	H	L	H	on	off	on	off	off	on	on	off	L
H	H	H	L	on	off	on	off	on	off	off	on	L
H	H	H	H	on	off	on	off	on	off	on	off	L
Figure 22: CMOS OR-AND-INVERT (OAI) gate: (a) circuit diagram; (b) function table.
Moslem Amiri, Václav Přenosi
Design of Digital Systems II
32 / 53
CMOS Logic: AND-OR-INVERT, OR-AND-INVERT Gates
Figure 23: Logic diagram for CMOS OAI gate shown in Fig. 22.
• CMOS AOI and OAI gates are very appealing
• They perform two levels of logic with one level of delay
• HDL synthesis tools can automatically convert AND/OR logic into AOI gates when appropriate
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CMOS Logic: Transmission Gates
• CMOS transmission gate
• A p-channel and n-channel transistor pair connected together to form a logic-controlled switch
• In Fig. 24
• Input signals EN and EN_L are always at opposite levels
• Once the gate is enabled, propagation delay from A to B (or vice versa) is very short
• Because of their short delays and simplicity, these gates are often used internally in larger-scale CMOS devices such as multiplexers and flip-flops
/EN
normally complementary
EN-
Figure 24: CMOS transmission gate.
Moslem Amiri, Vaclav Přenosi
Design of Digital Systems II
34 / 53
CMOS Logic: Transmission Gates
		[						
D	H							
	—1					L		
3-						r		
								
Figure 25: Two-input multiplexer using CMOS transmission gates.
• In Fig. 25
• When S is LOW, X input is connected to Z output
• When S is HIGH, Y is connected to Z
Moslem Amiri, Václav Přenosi
Design of Digital Systems II
October, 2012
35 / 53
CMOS Logic: Transmission Gates
• In transmission gate
• An "on" p-channel cannot conduct a LOW voltage between A and B very well
• An "on" n-channel cannot conduct a HIGH voltage between A and B very well
• But parallel transistors cover entire voltage range fine
• Hence two transistors are used
/en
normally complementary
en.
Moslem Amiri, Václav Přenosil
Design of Digital Systems II
October, 2012
36 / 53
CMOS Logic: Schmitt-Trigger Inputs
HIGH
undefined
LOW
r - t —i
T
1.5 3.5 5.0
LOW     undefined HIGH
Figure 26: Typical input-output transfer characteristic of a CMOS inverter.
Moslem Amiri, Vaclav Přenosi
Design of Digital Systems II
37 / 53
CMOS Logic: Schmitt-Trigger Inputs
• A Schmitt trigger is a circuit that uses feedback internally to shift switching threshold depending on whether input is changing from LOW to HIGH or from HIGH to LOW
(a)
(b)
- IT>0-
Figure 27: A Schmitt-trigger inverter: (a) input-output transfer characteristic; (b) logic symbol.
Moslem Amiri, Vaclav Přenosí
Design of Digital Systems II
38 / 53
CMOS Logic: Schmitt-Trigger Inputs
In Fig. 27
• Switching threshold for positive-going input changes (Vr+) is 2.9 V, and for negative-going input changes (Vt-) is 2.1 V
• Difference between the two thresholds is called hysteresis
• Schmitt-trigger inverter provides about 0.8 V of hysteresis
Moslem Amiri, Vaclav Přenosi
Design of Digital Systems II
39 / 53
CMOS Logic: Schmitt-Trigger Inputs
Figure 28: Device operation with slowly changing inputs: (a) a noisy, slowly changing input; (b) output produced by an ordinary inverter; (c) output produced by an inverter with 0.8 V of hysteresis.
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CMOS Logic: Schmitt-Trigger Inputs
• In Fig. 28
• (a) shows an input signal with long rise and fall times and about 0.5 V of noise on it
• An ordinary inverter, without hysteresis, has same switching threshold for both positive-going and negative-going transitions, Vj ~ 2.5 V
• Ordinary inverter responds to noise, producing multiple output changes each time noisy input voltage crosses switching threshold
• A Schmitt-trigger inverter does not respond to noise, because its hysteresis is greater than noise amplitude
• Schmitt-trigger inputs have better noise immunity than ordinary gate inputs for signals with transmission-line reflections or long rise and fall times
• Such signals occur in physically long connections, such as input-output buses and computer interface cables
Moslem Amiri, Václav Přenosi
Design of Digital Systems II
41 / 53
CMOS Logic: Three-State Outputs
• Logic outputs have two normal states, LOW (0) and HIGH (1)
• Some outputs have a third electrical state that is not a logic state, called high-impedance, Hi-Z, or floating state
• In this state, output behaves as if it is not connected to circuit
• An output with three possible states is called a three-state output or a tri-state output
• Three-state devices have an extra input, called "output enable" or "output disable," for placing device's output(s) in high-impedance state
• A three-state bus is created by wiring several three-state outputs together
• At most one output should be enabled at any time
Moslem Amiri, Vaclav Přenosi
Design of Digital Systems II
42 / 53
CMOS Logic: Three-State Outputs
• The most basic three-state device is three-state buffer (= three-state driver)
(a)
en a
a a
out
(b)
en	a	b	c	d	Q1	Q2 out
L	L	H	H	L	off	off Hi-z
L	H	H	H	L	off	off Hi-z
H	L	L	H	H	on	off L
H	H	L	L	L	off	on H
(c)
out
Figure 29: CMOS three-state buffer: (a) circuit diagram; (b) function table; (c) logic symbol.
Moslem Amiri, Vaclav Přenosi
Design of Digital Systems II
43 / 53
CMOS Logic: Three-State Outputs
• Devices with three-state outputs are designed so that output-enable delay (Hi-Z to LOW or HIGH) is somewhat longer than output-disable delay (LOW or HIGH to Hi-Z)
• Thus, if a control circuit activates one device's output-enable input and simultaneously deactivates a second's, the second device is guaranteed to enter Hi-Z state before the first places a HIGH or LOW level on bus
• If two three-state outputs on the same bus are enabled at the same time and try to maintain opposite states, a nonlogic voltage is produced on bus
• If fighting is only momentary, devices probably will not be damaged
• But large current drain through tied outputs can produce noise pulses that affect circuit behavior elsewhere in system
Moslem Amiri, Václav Přenosí
Design of Digital Systems II
44 / 53
CMOS Logic: Open-Drain Outputs
• p-channel transistors in CMOS output structures provide active pull-up
• They actively pull up output voltage on a LOW-to-HIGH transition
• These transistors are omitted in gates with open-drain outputs
(a)
(b)
A	B	Ql	Q2	Z
L	L	off	off	open
L	H	off	on	open
H	L	on	off	open
H	H	on	on	L
(c)
Figure 30: Open-drain CMOS NAND gate: (a) circuit diagram; (b) function table; (c) logic symbol.
• In Fig. 30, drain of topmost n-channel is left unconnected internally • If output is not LOW, it is "open"
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CMOS Logic: Open-Drain Outputs
• An open-drain output requires an external pull-up resistor to provide passive pull-up to HIGH level
Figure 31: Open-drain CMOS NAND gate driving a load.
Moslem Amiri, Václav Přenosil
Design of Digital Systems II
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CMOS Logic: Open-Drain Outputs
• For the highest possible speed, an open-drain output's pull-up resistor should be as small as possible
o This minimizes RC time constant for LOW-to-HIGH transitions (rise time)
• The minimum resistance is determined by open-drain output's maximum sink current, loLmax
• E.g., in HC- and HCT-series CMOS
5.0 V
loLmax = 4 mA —> pull-up resistormin = ^—- = 1.25 /eft
• Since this is an order of magnitude greater than "on" resistance of p-channel transistors, LOW-to-HIGH output transitions are much slower for an open-drain gate than for standard gate with active pull-up
Moslem Amiri, Václav Přenosi
Design of Digital Systems II
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CMOS Logic: Open-Drain Outputs
• Example: in Fig. 31
• Open-drain gate is HC-series CMOS —> "on" resistance of output in LOW state = 80 ft
• Pull-up resistance — 1.5 /eft
• Load capacitance — 100 pF
RC time constant for a HIGH-to-LOW transition — output's fall time
= 80 ft x 100 pF = 8 ns
RC time constant for a LOW-to-HIGH transition — output's rise time
= 1.5 /eft x 100 pF = 150 ns
Figure 32: Rising and falling transitions of an open-drain CMOS output.
Moslem Amiri, Václav Přenosil Design of Digital Systems II October, 2012
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CMOS Logic: Multisource Buses
Open-drain outputs can be tied together to allow several devices, one at a time, to put information on a common bus
• At any time all but one of outputs are in their HIGH (open) state
• Control circuitry selects particular device that is allowed to drive the bus at any time
In Fig. 33
• At most one control bit is HIGH at any time, enabling complement of corresponding data bit to be passed through bus
DATAOUT
Datal Enablel
Data2 Enable2
Data3 Enable3
Data4 Enable4
Data5 Enable5
Data6 Enable6
Data7 Enable7
Data8 Enable8
Figure 33: Eight open-drain outputs driving a bus.
Moslem Amiri, Vaclav Přenosi
Design of Digital Systems II
October, 2012
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CMOS Logic: Wired Logic
• If outputs of several open-drain gates are tied together with a single pull-up resistor, wired logic is performed
• An AND function is obtained, since wired output is HIGH iff all of individual gate outputs are HIGH (open)
• Any output going LOW is sufficient to pull wired output LOW
vcc
Figure 34: Wired-AND function on three open-drain NAND-gate outputs.
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CMOS Logic: Wired Logic
• In Fig. 34
• If any of individual 2-input NAND gates has both inputs HIGH, it pulls wired output LOW
• Otherwise, pull-up resistor R pulls wired output HIGH
• Wired logic cannot be performed using gates with active pull-up
• Fighting: Two such outputs wired together and trying to maintain opposite logic values result in a very high current flow and an abnormal output voltage
• Exact output voltage depends on relative strengths of fighting transistors
• If outputs fight continuously for more than a few seconds, chips can get hot enough to sustain internal damage
Moslem Amiri, Vaclav Přenosi
Design of Digital Systems II
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CMOS Logic: Wired Logic
Figure 35: Two outputs trying to maintain opposite logic values on the same line
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References
^ John F. Wakerly, Digital Design: Principles and Practices (4th Edition), Prentice Hall, 2005.
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