Design of Digital Systems II Sequential-Circuit Design with Verilog Moslem Amiri, Vaclav Prenosil Embedded Systems Laboratory Faculty of Informatics, Masaryk University Brno, Czech Republic amiriOmail.muni.cz prenosilOfi.muni.cz December, 2012 Clocked Circuits • Majority of Verilog-based digital design is directed to clocked, synchronous systems that use edge-triggered flip-flops • Like combinational behavior, edge-triggered behavior is specified using always blocks • Difference between combinational and edge-triggered behavior is in sensitivity list of always block • Keyword posedge or negedge is placed in front of signal name to indicate that the statements in block should be executed only at positive (rising) or negative (falling) edge of named signal Table 1: Behavioral Verilog for a positive-edge-triggered D flip-flop. module VrposDff(CLK, D, Q); input CLK, D; output Q; reg Q; always ® (posedge CLK) Q <= D; endmodule Moslem Amiri, Václav Přenosi Design of Digital Systems II 2/25 Clocked Circuits Table 2: Behavioral Verilog for a positive-edge-triggered D flip-flop with preset and clear. module Vrposdffpc(CLK, PR_L, CLR_L, D, Q); input CLK, PR.L, CLR.L, D; output Q; reg Q; always @ (posedge CLK or negedge PR_L or negedge CLR_L) if (PR_L==0) Q<= 1; else if (CLR_L==0) Q <= 0; else Q <= D; endmodule » Tab. 2 models a positive edge-triggered D flip-flop with asynchronous active-low preset and clear inputs • An edge-sensitivity keyword, negedge, is applied to a level, asynchronous input » Verilog compilers are set up to recognize this particular representation of edge-triggered-plus-asynchronous behavior, and in synthesis they will pick up right flip-flop component to implement it Moslem Amiri, Václav Přenosi Design of Digital Systems II 3/25 Clocked Circuits Table 3: Two modules for a positive-edge-triggered D flip-flop with a QN output. module VrposDffQN1(CLK, D, q, QN); input CLK, D; output Q, QN; reg Q, QN; always @ (posedge CLK) begin Q <= D; QN <= !D; end endmodule module VrposDffQN2(CLK, D, Q, QN) ; input CLK, D; output Q, QN; reg Q, QN; always <§ (posedge CLK) q <= D; always @ (q) qN <= !Q; endmodule • Tab. 3 • A typical synthesis tool infers two separate D flip-flops from the first module—one for Q and the other for QN • For the second module, QN is generated from Q using an inverter 4/25 Clocked Circuits • Always use nonblocking assignments (<=) in sequential always blocks • In programs with multiple sequential always blocks using blocking assignments (=), simulation results can vary depending on the order in which the simulator chooses to execute those blocks • Using nonblocking assignments ensures that righthand sides of all assignments are evaluated before new values are assigned to any of lefthand sides o This makes results independent of order in which righthand sides are evaluated Moslem Amiri, Václav Přenosi Design of Digital Systems II 5/25 Clocked Circuits Table 4: Clock generation within a test bench. "timescale 1 ns / 1 ns module mclkgen(MCLK); output MCLK; reg MCLK; initial begin MCLK =1; // Start clock at 1 at time 0 end always begin // 10 ns clock generation #6 MCLK =0; // 6 ns HIGH #4 MCLK =1; end; // 4 ns LOW endmodule • Tab. 4 shows generation of a 100-MHz clock with a 60% duty cycle o At time 0, MCLK is set to 1 by initial block • Then, always block waits 6 ns, sets MCLK to 0, waits 4 ns, sets MCLK to 1, and repeats forever • "timescale directive is used to set up the simulator both a default time unit and a precision of 1 ns 6/25 State-Machine Design with Verilog • There are many possible coding styles for creating state machines in Verilog, including using no consistent style at all • Without discipline of a consistent coding style, it is easy to write syntactically correct code where simulator's operation, synthesized hardware's operation, and what we think the machine should be doing are all different • In Verilog state-machine coding style, code is divided into three parts • State memory • This can be specified in behavioral form using an always block that is sensitive to a signal edge • Or it can use a structural style with explicit flip-flop instantiations • Next-state (excitation) logic • This is written as a combinational always block whose sensitivity list includes machine's current state and inputs • This block usually contains a case statement that enumerates all values of current state • Output logic • This is another combinational always block that is sensitive to current state and inputs • It may or may not include a case statement, depending on complexity of 3m Amiri, Václav^i^enosil ' 7/25 State-Machine Design with Verilog Next-State Logic State Memory always © (A, B, Sreg) begin case (Sreg) INIT: if (A==0) Snext - AO; else Snext = Al; Snext always © (po edge CLOCK) Sreg <= Sn xt; Sreg Output Logic always S (Sreg) case (Sreg) INIT, AO, Al; Z = 0; 0K0, OKI: Z = i; default Z = 0; endcase Figure 1: Moore state-machine structure implied by Verilog coding style. • Detailed coding within each section may very • When there is a tight coupling of next-state and output-logic specifications, it may be desirable to combine them into a single combinational always block, and into a single case statement • When pipelined outputs are used, output memory could be specified along with state memory, or a separate process or structural code could be used Moslem Amiri, Václav Přenosi Design of Digital Systems II December, 2012 8/25 A Verilog State-Machine Example • Design a clocked synchronous state machine with two inputs, A and B, and a single output Z that is 1 if • A had the same value at each of two previous clock ticks, or • B has been 1 since the last time that the first condition was true Otherwise, output should be 0 • One approach to writing a program is to construct a state and output table by hand and then manually convert it into a corresponding program Table 5: State and output table for the example state machine. A B s 00 01 11 10 Z INIT AO AO A1 A1 0 AO OKO OKO A1 A1 0 A1 AO AO 0K1 0K1 0 OKO OKO OKO 0K1 A1 1 OK1 AO OKO 0K1 0K1 1 s* Moslem Amiri, Václav Přenosil Design of Digital Systems II 9/25 A Verilog State-Machine Example Table 6: Verilog program for state-machine example. module VrSHexC CLOCK, A input CLOCK, A, B; output Z; rog Z; reg [2:0] Sreg, Snext parameter [2:0] INIT : AO Al = 3'bOOO, = 3'bOOl, - 3'bOlO, - 3'bOll, - 3'blOO; // State register and next state // Define the states always @ (posedge CLOCK) // Cre; Sreg <= Snext; the state memory always <9 (A, D, Sreg) r-ase (Sreg) IKIT: if (A==0) .V'.: // Next-state logii AC: If (A==0) if CA—0) else if (A==0) Snext = AO; Snext - Al; Snext - 0KO; Soest = Al; Snext = AO; Snext = OKI; Snext = OKO; í—1) && (B- else if C(A==0) && (B==0)) else if UA==0) M (B= -0)) Snext - Snext = Snext = =1)) Snext = QKO; OKI, default Snex endcase end always Q (Sreg) case (Sreg) INIT, AO, Al OKO, OKI: default endcase endmodule // Output logic s 00 01 11 10 Z INIT AO AO A1 A1 0 AO OKO OKO A1 A1 0 A1 AO AO OK1 OK1 0 OK0 OKO OKO OK1 A1 1 OK1 AO OKO OK1 OK1 1 Moslem Amiri, Václav Přenosil Design of Digital Systems II 10 / 25 A Verilog State-Machine Example • First always block (state memory creation) in Tab. 6 • During synthesis, positive-edge-triggered D flip-flops are inferred for Sreg • A synchronous or asynchronous RESET signal is easily provided as shown in Tab. 7 Table 7: Synchronous and asynchronous reset for state machines in Verilog. // State memory with active-high synchronous reset always @ (posedge CLOCK) // Create state memory if (RESET==1) Sreg <= INIT; else Sreg <= Snext; // State memory with active-high asynchronous reset always (§ (posedge CLOCK or posedge RESET) // Create state memory if (RESET==1) Sreg <= INIT; else Sreg <= Snext; Moslem Amiri, Václav Přenosi Design of Digital Systems II 11 / 25 A Verilog State-Machine Example • Second always block (next-state logic) in Tab. 6 • default case at the end handles unused states, but not uncovered input combinations in other cases • In each case, an if statement and a final else is used to ensure that a value is always assigned to Snext • If there were any state/input combinations in which no value was assigned to Snext, Verilog compiler would infer an unwanted latch for Snext • Variations ° To establish a default next state for machine if case fails to cover all state/input combinations, precede case statement with "Snext = INIT" • When most transitions stay in current state, case statement can be preceded by "Snext = Sreg" • Preceding with "Snext = 3'bx" is another variation which is useful in simulation to detect unspecified state/input combinations Moslem Amiri, Václav Přenosi Design of Digital Systems II 12 / 25 A Verilog State-Machine Example • Third always block (output logic) in Tab. 6 • Handles machine's single Moore output, Z, which is set to a value as a function of current state • To define Mealy output, output should be a function of inputs as well as state in each enumerated case • Inputs should also be added to sensitivity list of always block • Pipelined outputs o In design of high-speed circuits, it is often necessary to ensure that state-machine outputs are available as early as possible and do not change during each clock period • One way to get this behavior is to encode state so that state variables themselves serve as outputs • Called output-coded state assignment • It yields a Moore machine in which output logic is wires • Another approach is to design state machine so that outputs during one clock period depend on state and inputs during previous clock period • Called pipelined outputs • Obtained by attaching another stage of memory (flip-flops) to a machine's outputs Moslem Amiri, Václav Přenosi Design of Digital Systems II 13 / 25 A Verilog State-Machine Example inputs: Next-state Logic clock input Output Pipeline Memory clock input pipelined ' outputs clock signal • Figure 2: Mealy machine with pipelined outputs. • In our example Verilog state machine, the module defines a Moore-type state machine with the structure shown in Fig. 1 • We can convert the machine to have pipelined outputs with the structure shown in Fig. 3 o To do this, we need only to declare a "next-output" variable Zn and replace the original Verilog state-memory and output code with code shown in Tab. 8 14 / 25 A Verilog State-Machine Example Next-State Logic t always @ (A, B, Sreg) begin case (Sreg) INIT: if (A==0) Snext = AO; else Snext = Al; State Memory al.ays 8 (posedge CLOCK) Sreg Output Logic always © (Snext) case (Snext) INIT, AO, All Zn = 0; 0K0, OKI: Zn = 1; default Zn = 0; endcase Figure 3: Verilog state machine with pipelined outputs. State Memory Next-State Logic 1 t always 0 (A, B, Sreg) begin case (Sreg) INIT: if (A==0) Snext = AO; else Snext = Al; always IS (posedge CLOCK; Sreg <= Snext; —i Sreg Output Logic always © (Sreg! case (Sreg) INIT, AO, Al: Z = 0: □KO, OKI: Z = 1; default Z = 0; endcase Moslem Amiri, Václav Přenosil Design of Digital Systems II 15 / 25 A Verilog State-Machine Example Table 8: Verilog pipelined output code. always S (posedge CLOCK) // Create output register — this code Z <= Zn; // could be combined with state-memory code if desired always <§ (Snext) // Output logic case (Snext) BUT, AO, Al: Zn = 0; 0KO, OKI: Zn = 1; default Zn = 0; endcase • New machine's behavior is indistinguishable from that of original machine, except for timing • We have reduced propagation delay from CLOCK to Z by producing Z directly on a register output • But we have increased setup-time requirements of A and B to CLOCK • In addition to their propagation delay through next-state logic, changes in A and B must also get through output logic in time to meet setup time requirement of output flip-flop's D input Moslem Amiri, Václav Přenosi Design of Digital Systems II 16 / 25 A Verilog State-Machine Example • Direct Verilog coding without a state table • It is possible to write a Verilog program directly, without writing out a state table by hand • Design a clocked synchronous state machine with two inputs, A and B, and a single output Z that is 1 if • A had the same value at each of two previous clock ticks, or • B has been 1 since the last time that the first condition was true Otherwise, output should be 0 • We need to have a register that keeps track of A (LASTA) • Three states must be defined • INIT • LOOKING: still looking for a match o OK: got a match or B has been 1 since last match Moslem Amiri, Vaclav Přenosi Design of Digital Systems II 17 / 25 A Verilog State-Machine Example Table 9: Simplified Verilog state-machine design. module VrSMexaC CLOCK, RESET, A, B, Z ); input CLOCK, RESET, A, E; output Z; wire Z; // declared as wire for continuous assignment reg LASTA; // LASTA holds last value of A reg [1:0] Sreg, Snext; // State register and next state parameter [1:0] INIT = 2'b00, // Define the states LOOKING = 2'blO, DK = 2'bll; always @ (posedge CLOCK) begin // State memory (with sync, reset) if (RESET==1) Sreg <= INIT; else Sreg <= Snext; LASTA <= A; end always @ (A, B, LASTA, Sreg) begin // Next-state logic case (Sreg) INIT: Snext - LOOKING; LOOKING: if (A==LASTA) Snext = OK; else Snext = LOOKING; OK; if (B==l I I A==LASTA) Snext = OK; else Snext = LOOKING; default Snext = INIT; endcase end assig Z = (Sreg==0K) ? 1 endmodule // Output logic Moslem Amiri, Václav Přenosi Design of Digital Systems II 18 / 25 A Verilog State-Machine Example • Tab. 9 • First always block creates both state memory and LASTA register • Second one creates next-state logic using our simplified approach • Z output is a simple combinational decode of OK state, so it is created using a continuous-assignment statement Moslem Amiri, Václav Přenosi Design of Digital Systems II 19 / 25 More Verilog State-Machine Examples • Ones-counting machine • Design a clocked synchronous state machine with two inputs, X and Y, and one output, Z • Output should be 1 if the number of 1 inputs on X and Y since reset is a multiple of 4, and 0 otherwise • We can write a Verilog module for this problem directly, without constructing a state table Table 10: Verilog module for a ones-counting machine. module Vronescnt( CLDCK, RESET, X, Y, Z ); input CLOCK, RESET, X, Y; output Z; wire Z; // declared as wire for continuous assignment reg [1:0] COUHT, NEXTCNT; // Current and next count, modulo 4 parameter [1:0] ZERO = 2'bOO; always @ Cposedge CLOCK) // State memory (with sync, reset) if (RESET==1) COUNT <= ZERO; else COUNT <= NEXTCNT; always