Design of Digital Systems II Sequential Logic Design Practices (1) Moslem Amiri, Vaclav Prenosil Embedded Systems Laboratory Faculty of Informatics, Masaryk University Brno, Czech Republic amiriOmail.muni.cz prenosilOfi.muni.cz December, 2012 Timing Diagrams and Specifications CLOCK J flip-flop outputs combinational outputs flip-flop inputs —I rffpd l— i 'elk ■ comb setup-time margin nur setup hold Figure 1: A detailed timing diagram showing propagation delays and setup and hold times with respect to the clock. 2/63 Moslem Amiri, Václav Přenosi Timing Diagrams and Specifications • In Fig. 1 • First line shows system clock and its nominal timing parameters • Second line shows that flip-flops change their outputs at some time between rising edge of CLOCK and time tffpd afterward • External circuits that sample these signals should not do so while they are changing • Third line shows tcomb required for flip-flop output changes to propagate through combinational logic elements, such as flip-flop excitation logic • Excitation inputs of flip-flops and other clocked devices require a setup time of tsetup as shown in fourth line a For proper circuit operation: tdk - tffpd - tcomb > tsetup • Timing margins indicate how much "worse than worst-case" the individual components of a circuit can be without causing circuit to fail • Well-designed systems have positive, nonzero timing margins • Setup-time margin: tclk - tffpd{max) - tcomb{max) - tsetup • For proper circuit operation: tffpd(m!n) + tcomb(m!n) > thotd » Hold-time margin: tffpd{mm) + tcomb{mm) - thM Moslem Amiri, Václav Přenosil Design of Digital Systems II 3/63 Timing Diagrams and Specifications • In most circuits, there are timing differences between different flip-flop inputs or combinational-logic signals • E.g., one flip-flop's Q output may be connected directly to another flip-flop's D input • tCOmb for that path is zero, while another's may go through a long combinational path before reaching a flip-flop input o When proper synchronous design methodology is used, these relative timings are not critical, since none of these signals affect state of circuit until a clock edge occurs • Merely finding longest delay path in one clock period to determine whether circuit will work is enough • Requires analyzing several different paths in order to find worst-case one Moslem Amiri, Václav Přenosi Design of Digital Systems II 4/63 Timing Diagrams and Specifications Figure 2: Functional timing of a synchronous circuit. • Functional timing diagram shows only functional behavior and is not concerned with actual delay amounts • Lining up everything on clock edge allows timing diagram to display more clearly which functions are performed during each clock period • Shading or cross-hatching is used to indicate "don't-care" signal values Moslem Amiri, Václav Přenosi Design of Digital Systems II 5/63 SSI Latches and Flip-Flops • SSI latches and flip-flops have been eliminated to a large extent in modern designs as their functions are embedded in PLDs and FPGAs • Nevertheless, some of them still appear in many digital systems 2 PR D Q >CLK Q CLR 5 3 ^6 ho A, 74x74 12 PR D Q >CLK Q CLR 9 11 ^8 J- 74x109 2 PR J Q >CLK K Q CLR 6 4 ^7 74x109 14 PR J Q 10 12 >CLK 13^ K Q ^9 CLR ?« 3 PR J Q >CLK K Q CLR 5 1 ^ 2 ^6 11 PR J Q 9 13^ >CLK 12 K Q ^7 CLR ?H Figure 3: Pinouts for SSI latches and flip-flops. 74x375 1,2C 1Q 1D 1Q 2Q 2D 2Q 3,4C 3Q 3D 3Q 4Q 4D 4Q Moslem Amiri, Václav Přenosil Design of Digital Systems II 6/63 SSI Latches and Flip-Flops • In Fig. 3 • The only latch is 74x375, which contains four D latches • Because of pin limitations, latches are arranged in pairs with a common C control line for each pair • The most important device is 74x74 • It contains two independent positive-edge-triggered D flip-flops with preset and clear inputs • 74x109 is a positive-edge-triggered J-K flip-flop with an active-low K input • Another J-K flip-flop is 74x112, which has an active-low clock input Moslem Amiri, Václav Přenosi Design of Digital Systems II 7/63 • A common application of bistables and latches is switch debouncing • Switches connected to sources of constant logic 0 and 1 are often used in digital systems to supply user inputs • A simple make or break operation done by slow-moving humans, has several phases in high-speed digital logic +5V (a) push first contact bounce (b) +5V A SW_L GND DSW 0 n u Figure 4: Switch input without debouncing. 8/63 Switch Debouncing • Fig. 4 shows how a single-pole, single-throw (SPST) switch is used to generate a single logic input • After wiper hits bottom contact, it bounces a few times before finally settling o Results in several transitions on SW_L and DSW • This behavior is called contact bounce • Typical switches bounce for 10-20 ms, a very long time compared to switching speeds of logic gates • Contact bounce is a problem if a switch is used to count or signal some event • We must provide a circuit to debounce switch Moslem Amiri, Vaclav Přenosi Design of Digital Systems II 9/63 Switch Debouncing 74LS04 74LS04 push sw 1^ Sw-L -1^ DSW VOH - push SW j (b) SW L GND-- ^OH — GND — first contact bounce 1 n DSW Figure 5: Switch input using a bistable for debouncing. Moslem Amiri, Václav Přenosi Design of Digital Systems II 10 / 63 Switch Debouncing • Fig. 5 shows a switch debouncing application for bistable element • This circuit uses a single-pole, double-throw (SPDT) switch • Before button is pushed • Top contact holds SW at 0 V —> a valid logic 0 o When button is pushed and contact is broken • Feedback in bistable holds SW at Vol —> still a valid logic 0 • Vol = output low voltage (< 0.5 V for TTL) • When wiper hits bottom contact • Suddenly, SW_L is shorted to ground • A short time later, forced logic 0 on SW_L propagates through two inverters of bistable • At this point, top inverter output is no longer shorted to ground • Feedback in bistable maintains logic 0 on SW_L even if wiper bounces off bottom contact » Advantages of this circuit o It has a low chip count • No pull-up resistors are required • Both polarities of input signal (active-high and active-low) are produced • In situations where momentarily shorting gate outputs must be avoided, a S — R latch and pull-up resistors are used Moslem Amiri, Václav Přenosil Design of Digital Systems II 11 / 63 Switch Debouncing Moslem Amiri, Vaclav Prenosil Design of Digital Systems II 12 / 63 Multibit Registers and Latches • A collection of two or more D flip-flops with a common clock input is called a register clr_l -ilLo^o (4) d q >clk q clr (2) _( 0 - 1q - 1q_l >clk clr 1q 1d 1q 2q 2d 2q 3d 3q 3q 4q 4q Figure 7: The 74x175 4-bit register: (a) logic diagram, including pin numbers for a standard 16-pin dual in-line package; (b) traditional logic symbol. 13 / 63 Moslem Amiri, Václav Přenosil Multibit Registers and Latches • In 74x175, both CLK and CLR_L are buffered before fanning out to four flip-flops • A device driving one of these inputs sees only one unit load instead of four • 74x174 is similar to 74x175, except that it eliminates active-low outputs and provides two more flip-flops instead 74x174 ->CLK -!-0 CLR 3 1D 2D 3D 4D 5D 6D 1Q 2Q 3Q 4Q 5Q 6Q 15 Figure 8: Logic symbol for the 74x174 6-bit register. 14 / 63 Multibit Registers and Latches • Many digital systems process information 8, 16, or 32 bits at a time • ICs that handle eight bits are very popular 15 / 63 Multibit Registers and Latches > clk oe 1d 1q 2d 2q 3d 3q 4d 4q 5d 5q 6d 6q 7d 7q 8d 8q Figure 9: The 74x374 8-bit register: (a) logic diagram, including pin numbers for a standard 20-pin dual in-line package; (b) traditional logic symbol. 16 / 63 Multibit Registers and Latches • 74x374 • It contains eight edge-triggered D flip-flops that all sample their inputs and change their outputs on rising edge of a common CLK input • Each flip-flop output drives a three-state buffer that in turn drives an active-high output • All of three-state buffers are enabled by a common active-low OE_L (output enable) input • Control inputs (CLK and OE_L) are buffered so that they present only one unit load to a device that drives them 17 / 63 Multibit Registers and Latches • 74x373 is a variation of 74x374 which uses D latches instead of edge-triggered flip-flops • Its outputs follow corresponding inputs whenever C is asserted and latch the last input values when C is negated 74x373 Figure 10: Logic symbol for the 74x373 8-bit latch. Moslem Amiri, Václav Přenosi Design of Digital Systems I December, 2012 18 / 63 Multibit Registers and Latches • 74x273 is another variation of 74x374 which has non-three-state outputs and no OE_L input • It uses pin 1 for an asynchronous clear input CLR_L 74x273 Figure 11: Logic symbol for the 74x273 8-bit register. Moslem Amiri, Václav Přenosi Design of Digital Systems II 19 / 63 Multibit Registers and Latches • 74x377 is an edge-triggered register like '374, but it does not have three-state outputs • Instead, pin 1 is used as an active-low clock enable input EN_L • If EN_L is asserted (LOW) at rising edge of clock, flip-flops are loaded from data inputs; otherwise, they retain their present values (a) (b) 74x377 8D [18] -0>CK CLK ■ -o— [19] 8Q Figure 12: The 74x377 8-bit register with gated clock: (a) logic symbol; (b) logical behavior of one bit. Moslem Amiri, Václav Přenosi Design of Digital Systems II 20 / 63 Registers and Latches in Verilog Table 1: Verilog behavioral module for a D latch. module VrDlatchC C, D, Q, QN ); input C, D; output q, QN; reg Q, QN; always @ (C or D or Q) begin if (C==l) Q <= D; else Q <= Q; QN <= !Q; end endmodule • Tab. 1 • We could omit "else Q <= Q" clause and get the same results • Such code would not say what to do when C is 0, so compiler would infer a latch • It is better coding style to use an explicit else clause for "latch closed" case Moslem Amiri, Václav Přenosi Design of Digital Systems II 21 / 63 Registers and Latches in Verilog Table 2: Behavioral Verilog for a positive-edge-triggered D flip-flop. module VrDff(CLK, D, Q); input CLK, D; output Q; reg Q; always @ (posedge CLK) q <= D; endmodule • To describe edge-triggered behavior in a flip-flop, we need to use Verilog's posedge or negedge keyword in sensitivity list of an always statement Moslem Amiri, Václav Přenosil Design of Digital Systems II 22 / 63 Registers and Latches in Verilog Table 3: Verilog module for a 16-bit register with many features. module Vrregl6( CLK, CLKEN, DE_L, CLR_L, D, q ); input CLK, CLKEN, 0E_L, CLR_L; input [1:16] D; output [1:16] Q; reg [1:16] iq; always © (posedge CLK or negedge CLR_L) if (CLR_L==0) iq <= 16'bO; else if (CLKEN==1) IQ <= D; else IQ <= IQ; assign Q = (0E_L==0) ? IQ : 16'bz; endmodule • Registers can be modeled by defining data inputs and outputs to be vectors, and additional functions can be included • Tab. 3 • Models a 16-bit register with three-state outputs and clock-enable, output-enable, and clear inputs 23 / 63 Sequential PLDs: Bipolar Sequential PLDs Moslem Amiri, Václav Přenosi Figure 13: PAL16R8 logic diagram. 24 / 63 Sequential PLDs: Bipolar Sequential PLDs • PAL16R8 • It is representative of first generation of sequential PLDs, which used bipolar (TTL) technology • It has eight primary inputs, eight outputs, and common clock and output-enable inputs, and fits in a 20-pin package • It has edge-triggered D flip-flops between AND-OR array and its eight outputs, 01-08 • Each flip-flop drives an output pin through a 3-state buffer • Registered output pins contain complement of signal produced by AND-OR array • Possible inputs to AND-OR array are eight primary inputs (11-18) and eight D flip-flop outputs • Connection from D flip-flop outputs into AND-OR array makes it easy to design shift-registers, counters, and general state machines • D flip-flop outputs are available to AND-OR array whether or not 01-08 three-state drivers are enabled • Internal flip-flops can go to a next state that is a function of current state even when 01-08 outputs are disabled Moslem Amiri, Václav Přenosi Design of Digital Systems II 25 / 63 Sequential PLDs: Bipolar Sequential PLDs • Many applications require combinational as well as sequential PLD outputs • There are a few variants of PAL16R8 without D flip-flops on some output pins • PAL16R6 • It has only six registered outputs • Two pins, 101 and 108, are bidirectional • They serve both as inputs and as combinational outputs with separate 3-state enables • Possible inputs to AND-OR array are eight primary inputs (11-18), six D flip-flop outputs, and two bidirectional pins (101, 108) Moslem Amiri, Vaclav Přenosi Design of Digital Systems II 26 / 63 Sequential PLDs: Bipolar Sequential PLDs Moslem Amiri, Václav Přenosil Figure 14: PAL16R6 logic diagram. 27 / 63 Sequential PLDs: Sequential GAL Devices • GAL16V8 electrically erasable PLD • Two "architecture-control" fuses are used to select among three basic configurations of this device O 16V8C ("complex") configuration, which was introduced in combinational section before © 16V8S ("simple") configuration, which provides a slightly different combinational logic capability Q 16V8R ("registered") configuration, which allows a flip-flop to be provided on any or all of outputs Moslem Amiri, Václav Přenosi Design of Digital Systems II 28 / 63 Sequential PLDs: Sequential GAL Devices Figure 15: 16V8R logic diagram. 29 / 63 Sequential PLDs: Sequential GAL Devices • In Fig. 15 • Circuitry inside each dotted box is called an output logic macrocell • Each macrocell may be individually configured to bypass flip-flop to produce a combinational output o It is possible to program the device to have any set of registered and combinational outputs, up to eight total Registered oe clk output logic macrocell Combinational oe clk output logic macrocell (a) _J*lr> Qni \y- E:E (b) Figure 16: Output logic macrocells for the 16V8R: (a) registered; (b) combinational. Moslem Amiri, Václav Přenosil Design of Digital Systems II 30 / 63 Sequential PLDs: Sequential GAL Devices Figure 17: Logic diagram for the 22V10. 31 / 63 Sequential PLDs: Sequential GAL Devices (a) CLK Registered sp I ar output logic macrocell (b) CLK Combinational sp + ar output logic macrocell Figure 18: Output logic macrocells for the 22V10: (a) registered; (b) combinational. » 22V10 • It does not have "architecture control" bits like 16V8's, but it can realize any function that is realizable with a 16V8, and more • Each output logic macrocell is configurable to have a register or not • A single product term controls output buffer • Every output has at least eight product terms available • More product terms are available on inner pins, with 16 available on each of two innermost pins Moslem Amiri, Václav Přenosi Design of Digital Systems II 32 / 63 Sequential PLDs: Sequential GAL Devices • 22V10 • Clock signal on pin 1 is also available as a combinational input to any product term • A single product term is available to generate a global, asynchronous reset signal that resets all internal flip-flops to 0 • A single product term is available to generate a global, synchronous preset signal that sets all internal flip-flops to 1 on rising edge of clock o It has programmable output polarity • However, in registered configuration, polarity change is made at output of D flip-flop. This affects details of programming when polarity is changed but does not affect overall capability of 22V10 Moslem Amiri, Václav Přenosi Design of Digital Systems II 33 / 63 Counters • A counter is a clocked sequential circuit whose state diagram contains a single cycle • Modulus of a counter is the number of states in the cycle • A counter with m states is modulo-m counter or a divide-by-m counter • The most commonly used counter type is an n-bit binary counter • It has n flip-flops and 2" states Figure 19: General structure of a counter's state diagram—a single cycle. 34 / 63 Counters: Ripple Counters • An n-bit binary counter can be constructed with just n flip-flops • In Fig. 20, each bit of counter toggles if and only if the immediately preceding bit changes from 1 to 0 • This corresponds to a normal binary counting sequence • When a particular bit changes from 1 to 0, it generates a carry to next most significant bit CLK ■ Q >T Q "I Q >T Q °-| ■ Q1 Q >T Q °-| ■ Q2 Q >T Q 0— Moslem Amiri, Václav Přenosil Figure 20: A 4-bit binary ripple counter. Design of Digital Systems II December, 2012 35 / 63 Counters: Synchronous Counters • A ripple counter requires fewer components than any other type of binary counter • But it is slower than any other type of binary counter • A synchronous counter uses T flip-flops with enable inputs CNTEN-CLK- EN EN EN EN Q >T ■ QO ■Q1 ■Q2 ■ Q3 Figure 21: A synchronous 4-bit binary counter with serial enable logic. 36 / 63 Counters: Synchronous Counters • In Fig. 21 • All of flip-flop clock inputs are connected to same common CLK signal • All of flip-flop outputs change at same time • CNTEN is a master count-enable signal • Each T flip-flop toggles if and only if CNTEN is asserted and all of lower-order counter bits are 1 • It is called a synchronous serial counter because combinational enable signals propagate serially from least significant to most significant bits • If clock period is too short, there may not be enough time for a change in counter's LSB to propagate to MSB • This problem is eliminated in synchronous parallel counters • A synchronous parallel counter is the fastest binary counter structure Moslem Amiri, Václav Přenosil Design of Digital Systems II 37 / 63 Counters: Synchronous Counters EN Q >T EN Q >T y- EN Q >T L> EN Q >T Figure 22: A synchronous 4-bit binary counter with parallel enable logic. Moslem Amiri, Václav Přenosil Design of Digital Systems II 38 / 63 Counters: MSI Counters and Applications • The most popular MSI counter is 74x163, a synchronous 4-bit binary counter with active-low load and clear inputs 74x163 10 3 > CLK CLR LD ENP ENT A QA B QB C QC D QD RCO 14 13 12 11 15 Figure 23: Traditional logic symbol for the 74x163. Moslem Amiri, Václav Přenosi Design of Digital Systems II 39 / 63 Counters: MSI Counters and Applications Table 4: State table for a 74x163 4-bit binary counter. Inputs Current State Next State CLR_L LD_L ENT ENP QD QC QB QA QD* QC* QB* QA* 0 X X X X X X X 0 0 0 0 1 0 X X X X X X D C B A 1 1 0 X X X X X QD QC QB QA 1 1 X 0 X X X X QD QC QB QA 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 1 0 0 1 0 1 1 1 1 0 0 1 0 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 0 1 1 1 1 0 1 0 0 0 1 0 1 1 1 1 1 0 1 0 1 0 1 1 0 1 1 1 1 0 1 1 0 0 1 1 1 1 1 1 1 0 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 0 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 Moslem Amiri, Václav Přenosil Design of Digital Systems II 40 / 63 Counters: MSI Counters and Applications Figure 24: Logic diagram for the 74x163 synchronous 4-bit binary counter, including pin numbers for a standard 16-pin dual in-line package. 41 / 63 Counters: MSI Counters and Applications • 74x163 • It uses D rather than T flip-flops to facilitate load and clear functions • Each D input is driven by a 2-input multiplexer consisting of an OR gate and two AND gates • Multiplexer output is 0 if CLR_L input is asserted, otherwise, top AND gate passes data input (A, B, C, or D) to output if LD_L is asserted • If neither CLR_L nor LD_L is asserted, bottom AND gate passes output of an XNOR gate to multiplexer output • XNOR gates perform counting function • One input of each XNOR is the corresponding count bit (QA, QB, QC, or QD) • Other input is 1, which complements count bit, if and only if both enables ENP and ENT are asserted and all of lower-order count bits are 1 • RCO (ripple carry out) signal indicates a carry from most significant bit position • It is 1 when all of count bits are 1 and ENT is asserted Moslem Amiri, Vaclav Přenosi Design of Digital Systems II 42 / 63 Counters: MSI Counters and Applications • Even though most MSI counters have enable inputs, they are often used in a free-running mode in which they are enabled countinuously 74x163 CLOCK■ +5 V > CLK O CLR RPU 10 0|LD ENP ENT A QA QB QC QD RCO 13 U1 -QA QB -QC -QD -RCO Figure 25: Connections for the 74x163 to operate in a free-running mode. Moslem Amiri, Vaclav Přenosi Design of Digital Systems II 43 / 63 Counters: MSI Counters and Applications • Fig. 26 shows resulting output waveforms for a free-running '163 • Starting with QA, each signal has half frequency of preceding one • A free-running '163 can be used as a divide-by-2, -4, -8, or -16 counter, by ignoring any unnecessary high-order output bits CLK QA QB QC QD RCO COUNT 10 11 12 13 14 15 Figure 26: Clock and output waveforms for a free-running divide-by-16 counter. Moslem Amiri, Václav Přenosil Design of Digital Systems I December, 2012 44 / 63 Counters: MSI Counters and Applications • '163 is fully synchronous • Its outputs change only on rising edge of CLK • 74x161 has same pinout but provides an asynchronous clear function; its CLR_L input is connected to asynchronous clear inputs of its flip-flops • 74x160 and 74x162 have same pinouts and functions as '161 and '163 • Except that counting sequence is modified to go to state 0 after state 9 • These are modulo-10 counters, called decade counters CLOCK COUNT — ~L \ \ \ \ \ \ / / / / / \ \ 1 / \ 1 \ 1 / 9 \ \ \ 0 1 2 3 4 5 6 7 8 0 Figure 27: Clock and output waveforms for a free-running divide-by-10 counter. 45 / 63 Counters: MSI Counters and Applications • In Fig. 27, although QD and QC outputs have one-tenth of CLK frequency, they do not have a 50% duty cycle • '163 is a modulo-16 counter, but it can be made to count in a modulus less than 16 • Use CLR_L or LD_L input to shorten normal counting sequence 74x163 CLOCK RPU 1 — >CLK O CLR ■O LD ENP 14 Q0 Q1 Q2 Q3 +5 V Figure 28: Using the 74x163 as a modulo-11 counter with the counting sequence 5, 6,..., 15, 5, 6,.... Moslem Amiri, Václav Přenosil Design of Digital Systems II December, 2012 46 / 63 Counters: MSI Counters and Applications o Fig. 28 shows one way of using '163 as a modulo-11 counter • RCO output, which detects state 15, is used to force next state to 5 • Circuit counts from 5 to 15, for a total of 11 states per counting cycle • Fig. 29 shows a different approach for modulo-11 counting with '163 74x163 CLOCK > CLK RPU 9 ■^O CLI LD QO Q1 Q2 Q3 74x00 CNT10_L U1 Figure 29: Using the 74x163 as a modulo-11 counter with the counting sequence 0,1,2,..., 10, 0,1,.... 47 / 63 • In general, to detect state N in a binary counter that counts from 0 to N, we need to AND only state bits that are 1 in binary encoding of N • Excess-3 code word for each decimal digit is the corresponding BCD code word plus OOII2 • Because excess-3 code words follow a standard binary counting sequence, standard binary counters can easily be made to count in excess-3 code Table 5: Decimal codes. Decimal digit BCD (8421) Excess-3 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 2 3 4 5 6 7 8 9 Moslem Amiri, Václav Přenosil Design of Digital Systems II December, 2012 48 / 63 Counters: MSI Counters and Applications • In Fig. 30, a NAND gate detects state 1100 and forces 0011 to be loaded as next state CLOCK ■ +5 V 74x163 10 > CLK O CLR O LD ENP ENT A B C D S11XX L QA QB QC QD RCO U1 74x00 ■ Q0 ■ Q1 ■ Q2 ■ Q3 Figure 30: A 74x163 used as an excess-3 decimal counter. Moslem Amiri, Václav Přenosi Design of Digital Systems II 49 / 63 Counters: MSI Counters and Applications • In Fig. 31, Q3 output has a 50% duty cycle, which may be desirable for some applications / \ \ / \ / \ \ / \ / \ \ n / / \ 1 1 / \ 1 \ 1 \ 1 8 9 10 11 12 \ 3 4 5 6 7 3 Figure 31: Timing waveforms for the '163 used as an excess-3 decimal counter. Moslem Amiri, Václav Přenosil Design of Digital Systems II 50 / 63 Counters: MSI Counters and Applications • A binary counter with a modulus greater than 16 can be built by cascading 74x163s as in Fig. 32 • In Fig. 32, RC04 output is asserted if and only if low-order '163 is in state 15 and CNTEN, master count-enable, is asserted • Scheme of Fig. 32 can be extended to build a counter with any desired number of bits CLOCK ■ RESETL■ LOADL■ CNTEN ■ DO ■ D1 ■ D2 ■ D3 ■ 1 >CLK O CLR 10 C|LD ENP ENT A B C D QA QB QC QD RCO U1 ■ Q0 ■ Q1 ■ Q2 ■ Q3 RC04 D4 ■ D5 ■ D6 ■ D7 ■ 74x163 >CLK O CLR 0|LD ENP ENT A B C D QA QB QC QD RCO U2 ■ Q4 ■ Q5 ■ Q6 ■ Q7 RCQ8 Figure 32: General cascading connections for 74xl63-based counters. 51 / 63 Counters: MSI Counters and Applications F — > clk i0 clr ld — ENP ENT — > clk clr ?-C ld — ENP -!i ENT -Q5 -Q6 Figure 33: Using 74x163s as a modulo-193 counter with the counting sequence 63,64, ...,255,63,64,.... 52 / 63 Counters: MSI Counters and Applications • Fig. 33 • It is a modulo-193 counter that counts from 63 to 255 • MAXCNT output detects state 255 and stops counter until GO_L is asserted • When GO_L is asserted, counter is reloaded with 63 and counts up to 255 again o Value of GO_L is relevant only when counter is in state 255 • To keep counter stopped, MAXCNT must be asserted in state 255 even while counter is stopped • In Fig. 24, both ENP and ENT enable inputs must be asserted for counter to count. However, ENT goes to ripple carry output as well • Therefore, in Fig. 33, low-order counter's ENT input is always asserted, its RCO output is connected to high-order ENT input, and MAXCNT detects state 255 even if CNTEN is not asserted • To enable counting, CNTEN is connected to ENP inputs in parallel • A NAND gate asserts RELOAD_L to go back to state 63 only if GO_L is asserted and counter is in state 255 Moslem Amiri, Václav Přenosi Design of Digital Systems II 53 / 63 Counters: MSI Counters and Applications • Another counter with functions similar to 74xl63's is 74x169 • '169 is an up/down counter • It counts in ascending or descending binary order depending on value of an input signal, UP/DN • '169 counts up when UP/DN is 1 and down when UP/DN is 0 74x169 2 > CLK UP/DN LD ENP ENT A QA B QB C QC D QD RCO 14 1 9^ 7_ 3 4 13 5 12 6 11 Figure 34: Logic symbol for the 74x169 up/down counter. Moslem Amiri, Václav Přenosil Design of Digital Systems II 54 / 63 Counters: Decoding Binary-Counter States • A binary counter may be combined with a decoder to obtain a set of 1-out-of-m-coded signals, where one signal is asserted in each counter state • This is useful when counters are used to control a set of devices where a different device is enabled in each counter state CLOCK RPU +5 V Figure 35: A modulo-8 binary counter and decoder. 55 / 63 Counters: Decoding Binary-Counter States \ \ n / \ V / \ r~ \_ V / \ i V / \ V V V / \ V / \ v V i / \ _ V i / \ 7 i / 0 1 2 3 4 5 v 6 1 0 1 2 Figure 36: Timing diagram for a modulo-8 binary counter and decoder, showing decoding glitches. Moslem Amiri, Václav Přenosi Design of Digital Systems II 56 / 63 Counters: Decoding Binary-Counter States • Fig. 36 • Decoder outputs may contain glitches on state transitions where two or more counter bits change, even though '163 outputs are glitch free and '138 does not have any static hazards • In a synchronous counter like '163, outputs don't change at exactly the same time • Also, multiple signal paths in a decoder like '138 have different delays • E.g., path from B to Y1_L is faster than path from A to Y1_L • Thus, even if input changes simultaneously from Oil to 100, decoder may behave as if input were temporarily 001, and Y1_L output may have a glitch • In most applications, decoder output signals are used as control inputs to registers, counters, and other edge-triggered devices • In such a case, decoding glitches are not a problem • They occur after clock tick • Glitches would be a problem if they were applied to something like inputs of an S — R latch Moslem Amiri, Vaclav Přenosi Design of Digital Systems II 57 / 63 Counters: Decoding Binary-Counter States • One way to clean up glitches in Fig. 36 is to connect '138 outputs to another register that samples stable decoded outputs on next clock tick • A less costly solution is to use an 8-bit "ring counter" which provides glitch-free decoded outputs directly CLOCK Figure 37: A modulo-8 binary counter and decoder with glitch-free outputs. Moslem Amiri, Vaclav Přenosi Design of Digital Systems II 58 / 63 Counters in Verilog Table 6: Verilog module for a 74xl63-like 4-bit binary counter. module Vr74xl63( CLK, CLR_L, LD_L, ENP, ENT, D, Q, RCO ); input CLK, CLR_L, LD_L, ENP, ENT; input [3:0] D; output [3:0] [J; output RCO; reg [3:0] Q; reg RCO; always S (posedge CLK) // Create the counter f-f behavior if (CLR_L ==0) q <= 4'bO; else if (LD_L == 0) Q <= D; else if ((ENT == 1) kk (ENP == D) Q <- Q + 1; else CJ <= Q; always @ (Q or ENT) if ((ENT == 1) kk (q else endmodule // Create RCO combinational output == 4'dlS)) RCO = 1; RCO = 0; > clk clr enp ent • In Tab. 6, usual state-machine coding style is not used • Since next-state logic is simple, it is put in the same always block with the edge-triggered flip-flop behavior 59 / 63 Counters in Verilog Table 7: Verilog code for a 74xl62-like 4-bit decimal counter. always @ (posedge CLK) // Create the counter f-f behavior if (!CLR_L0 else if C!LD_L) else if (ENT kk EKP kk (Q == else if CENT kk EKP) else q <= 4'bO; Q <= D; 'd9)) q <= 4'bO; q <= Q + 1; q <= q; always @ (q or EWT) // Create RCq combinational output if CENT kk (Q == 4'd9)) RCO = 1; else RCO = 0; > CLK CLR enp ent QD ■ -SCO . Moslem Amiri, Václav Přenosi Design of Digital Systems II 60 / 63 Counters in Verilog Table 8: Verilog code for the excess-3 decimal counting sequence. always @ (posedge CLK) if (!CLR_L) else if (!LD_L) else if (ENT M ENP kk else if CENT kk ENP) else // Create the counter f-f behavior Q <= 4'd3; Q <= D; (Q == 4'dl2)) Q <= 4'd3; Q <= Q + 1; q <= Q; always @ (q or ENT) // Create RCO combinational output if (ENT kk CQ == 4'dl2)) RCO = 1; else RCD = 0; Moslem Amiri, Václav Přenosi Design of Digital Systems II 61 / 63 Counters in Verilog Table 9: Verilog code for a 74xl69-like 4-bit up/down counter. always if ( else else else else always if else else @ (posedge CLK) // Create the counter f-f behavior ICLE.L ) if C!LD_L) if (!ENT_L kk !ENP_L kk UPDN) if (!ENT_L kk !ENP_L kk !UPDN) q <= 4'bO; Q <= D; Q <= Q + 1; q <= q - i; q <= Q; @ (q or ENT_L or UPDN) // Create RCCLL combinational output (IEWT.L kk UPDN kk (q == 4'dl5)) RCD.L = 0 if (!ENT_L kk !UPDN kk (Q == 4'dO )) RC0_L = 0 RCD.L = 1 Moslem Amiri, Václav Přenosil Design of Digital Systems II 62 / 63 References ^ John F. Wakerly, Digital Design: Principles and Practices (4th Edition), Prentice Hall, 2005. 63 / 63