Design of Digital Systems II Combinational Logic Design Practices (2) Moslem Amiri, Vaclav Prenosil Embedded Systems Laboratory Faculty of Informatics, Masaryk University Brno, Czech Republic amiriOmail.muni.cz prenosilOfi.muni.cz Fall, 2014 Decoders • A decoder is a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where input and output codes are different • Input code generally has fewer bits than output code • There is a one-to-one mapping from input code words into output code words a In a one-to-one mapping, each input code word produces a different output code word Decoder output code word Figure 1: Decoder circuit structure. Moslem Amiri, Václav Přenosi Design of Digital Systems II Fall, 2014 2/69 Decoders • Enable inputs must be asserted for decoder to perform its normal mapping function • Otherwise, it maps all input code words into a single, "disabled," output code word • Most commonly used input code is an n-bit binary code • An n-bit word represents one of 2" different coded values • Most commonly used output code is a 1-out-of-m code • m bits where one bit is asserted at any time Moslem Amiri, Václav Přenosi Design of Digital Systems II Fall, 2014 3/69 Decoders: Binary Decoders • Binary decoder is an n-to-2" decoder It has an n-bit binary input code and a l-out-of-2" output code 2-to-4 decoder 10 Y0 11 Y1 Y2 EN Y3 (a) I0' I0 11' 11 EN l> EN ■ (b) Y0 Y1 Y2 Y3 Figure 2: A 2-to-4 decoder: (a) inputs and outputs; (b) logic diagram. Moslem Amiri, Václav Přenosi Design of Digital Systems I 4/69 Decoders: Binary Decoders Table 1: Truth table for a 2-to-4 binary decoder. Inputs Outputs EN 11 10 Y3 Y2 Yl Y0 0 X X 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 • Input code of an n-bit binary decoder need not represent integers from 0 through 2" - 1 o E.g., it can be in Gray code (appropriately assign inputs to outputs) • It is not necessary to use all of outputs of a decoder, or even to decode all possible input combinations • E.g., a BCD decoder decodes only first ten binary input combinations 0000-1001 to produce outputs Y0-Y9 Moslem Amiri, Václav Přenosil Design of Digital Systems II Fall, 2014 5/69 Decoders: The 74x139 Dual 2-to-4 Decoder • 74x139 is a single MSI part containing two independent and identical 2-to-4 decoders 6/69 Decoders: The 74x139 Dual 2-to-4 Decoder Figure 3: The 74x139 dual 2-to-4 decoder: (a) logic diagram, including pin numbers for a standard 16-pin dual in-line package; (b) traditional logic symbol; (c) logic symbol for one decoder. Moslem Amiri, Václav Přenosi Design of Digital Systems II Fall, 2014 7/69 Decoders: The 74x139 Dual 2-to-4 Decoder • Outputs and enable input of '139 are active-low • Inverting gates are generally faster than noninverting ones • '139 has extra inverters on its select inputs • Without these inverters, each select input would present three AC or DC loads instead of one, consuming much more of fanout budget of device that drives it Table 2: Truth table for one-half of a 74x139 dual 2-to-4 decoder. Inputs Outputs G_L B A Y3_L Y2_L Y1_L YCLL 1 X X 1 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 1 Moslem Amiri, Václav Přenosil Design of Digital Systems II Fall, 2014 8/69 Decoders: The 74x138 3-to-8 Decoder Figure 4: The 74x138 3-to-8 decoder: (a) logic diagram, including pin numbers for a standard 16-pin dual in-line package; (b) traditional logic symbol. 9/69 Decoders: The 74x138 3-to-8 Decoder Table 3: Truth table for a 74x138 3-to-8 decoder. Inputs Outputs Gl G2A_L G2EĽL C B A Y7_L Y6-L Y5-L Y4_L Y3-L Y2_L Y1_L Y0_L 0 X X X x x 1 1 1 1 1 1 1 1 X 1 X X x x 1 1 1 1 1 1 1 1 X X 1 X x x 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 1 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 0 0 1 1 1 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 1 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 Moslem Amiri, Václav Přenosil Design of Digital Systems II Fall, 2014 10 / 69 Decoders: Cascading Binary Decoders • Multiple binary decoders can be used to decode larger code words Figure 5: Design of a 4-to-16 decoder using 74x138s. Moslem Amiri, Václav Přenosi Design of Digital Systems II Fall, 2014 11 / 69 Decoders: Cascading Binary Decoders • To handle larger code words, binary decoders can be cascaded hierarchically 12 / 69 Decoders: Cascading Binary Decoders - DEC0_L - DEC1_L - DEC2_L - DEC3_L - DEC4_L - DEC5_L - DECB_L - DEC7_L - DEC16_L DEC17_L DEC1S_L - DEC19_L - DEC21_L - DEC22_L - DEC23_L - DEC24_L - DEC25_L - DEC2B_L - DEC27_L - DEC2S_L DEC29_L - DEC31_L Figure 6: Design of a 5-to-32 decoder using 74x138s and a 74x139. Moslem Amiri, Václav Přenosil Design of Digital Systems II Fall, 2014 13 / 69 Decoders in Verilog Table 4: Structural-style Verilog module for the decoder in Fig. 2. module Vr2to4dec(I0, II, EN, YO, Yl, Y2, Y3); input 10, II, EN; output YO, Yl, Y2, Y3; wire N0TI0, N0TI1; INV Ul (NOTIO, 10); INV U2 (MOTU, II) ; AND3 U3 (YO, NOTIO, N0TI1, EN) AND3 U4 (Yl, 10, N0TI1, EN) AND3 UB (Y2, NOTIO, II, EN) AND3 U6 (Y3, 10, II, EN) endmodule 2-to-4 decoder 10 -ri>> 11 ^t>^ I0' I0 lľ h EN Moslem Amiri, Václav Přenosil Design of Digital Systems II 14 / 69 Decoders in Verilog Table 5: decoder. Functional-style Verilog module for a 74xl38-like 3-to-8 binary module Vr74xl38a(Gl, G2A_L, G2B_L, A, Y_L); input Gl, G2A_L, G2B_L; input [2:0] A; output [0:7] Y_L; reg [0:7] Y_L; always @ (Gl or G2A_L or G2B_L or A) begi if (Gl & ~G2A_L & ~G2B_L) case 0 1 2 3 4 5 6 7 (A) Y_L Y.L Y_L Y_L Y_L Y_L Y.L Y_L 8'b01111111; 8'blOllllll; B'bllOlllll; 8'blllOllll; B'bllllOlll; 8'blllllOll; 8'bllllllOl; 8'blllllllO; Y.L = 8'bllllllll; default: endcase else Y.L = 8'bllllllll; end endmodule Moslem Amiri, Vaclav Přenosi Design of Digital Systems II Fall, 2014 15 / 69 Decoders in Verilog • In Tab. 5 • Constants and inversions that handle the fact that two inputs and all outputs are active low are scattered throughout the code • While its true that most Verilog programs are written almost entirely with active-high signals, if we are defining a device with active-low external pins, we should handle them in a more systematic and easily maintainable way • Tab. 6 • Decoder function is defined in terms of only active-high signals • The design can be easily modified in just a few well-defined places if changes are required in external active levels Moslem Amiri, Václav Přenosi Design of Digital Systems II Fall, 2014 16 / 69 Decoders in Verilog Table 6: Verilog module with a maintainable approach to active-level handling. module Vr74xl3Sb(Gl, G2A_L, G2B_L, Input Gl, G2A_L, G2B_L; input [2:0] A; output [0:7] Y_L; reg G2A.G2B; reg [0:7] Y_L, Y; A, Y_L); alTOyS « (Gl or G2A_L or G2B_L or A G2A = ~G2A_L; // Convert inputs G2B = -G2B_L; Y_L = "Yj // Convert outputs if (Gl & G2A & G2B) Y) begin (A) Y = case 0 1 2 3 4 5 6 7 default endcase else Y = 8' end endmodule 8'blOOOOOOO; 8'bOlOOOOOO; 8'bOOlOOOOO; 8'bOOOlOOOO; 8'bOOOOlOOO; 8'bOOOOOlOO; 8'bOOOOOOlO; 8'bOOOOOOOl; Y = 8'bOOOOOOOO; Moslem Amiri, Václav Přenosi Design of Digital Systems II Fall, 2014 17 / 69 Decoders in Verilog Table 7: Hierarchical definition of 74xl38-like decoder with active-level handling. module Vr74xl38c(Gl, G2A.L, G2B_L, A, Y_L); input Gl, G2A_L, G2B_L; input [2:0] A; output [0:7] Y_L; wire G2A.G2B; wire [0:7] Y; assign G2A = "G2A_L; // Convert inputs assign G2B = ~G2B_L; assign Y_L = ~Y; // Convert outputs Vr3to8deca Ul (Gl, G2A, G2B, A, Y); endmodule Table 8: Verilog functional definition of an active-high 3-to-8 decoder. module Vr3to8deca(Gl, G2, G3, A, Y); input Gl, G2, G3; input [2:0] A; output [0:7] Y; reg [0:7] Y; always 15 (Gl or G2 or G3 or A) begin if (Gl Si G2 k G3) case (A) 0: Y = 8'blOOOOOOO; 1: Y = 8'b01000000; 2: Y = 8'bOOlOOOOO; 3: Y = 8'bOOOlOOOO; 4: Y = 8'bOOOOlOOO; 5: Y = 8'bOOOOOlOO; 6: Y - 8'bOOOOOOlO; 7: Y = 8'bOOOOOOOl; default: Y = 8'bOOOOOOOO; endcase else Y = 8'bOOOOOOOO; end endmodule Moslem Amiri, Václav Přenosi Design of Digital Systems II Fall, 2014 18 / 69 Decoders in Verilog module Vr74x138c — G1 YJ_[0:7] — G2A_L — G2B_L — A[2:0] module Vr74x138c module Vr3to8deca G1 G2A_L G2A G2B_L i-1 G2B A[2:0] G1 G2 G3 A[2:0] Y[0:7] Y[0:7] Y_L[0:7] (a) (b) Figure 7: Verilog module 74x138c: (a) top level; (b) internal structure usin module Vr3to8deca. Moslem Amiri, Vaclav Přenosi Design of Digital Systems II Fall, 2014 19 / 69 Decoders in Verilog Table 9: Behavioral Verilog definition for a 3-to-8 decoder. module Vr3to8decb{Gl, G2, G3, A, Y); input Gl, G2, G3; input [2:0] A; output [0:7] Y; rsg [0:7] Y; integer i; always @ (Gl or G2 or G3 or A) begin Y = 8'bOOOOOOOO; if (Gl & G2 & G3) for (i=0; i<=7; i=i+l) if (i == A) Y[i] = 1; end endmodule Moslem Amiri, Václav Přenosi Design of Digital Systems II Fall, 2014 20 / 69 Decoders: Seven-Segment Decoders • A seven-segment decoder has 4-bit BCD as its input code and "seven-segment code" as its output code a d (a) (b) Figure 8: Seven-segment display: (a) segment identification; (b) decimal digits. Moslem Amiri, Václav Přenosi Design of Digital Systems II Fall, 2014 21 / 69 Decoders: Seven-Segment Decoders Figure 9: The 74x49 seven-segment decoder: (a) logic diagram, including pin numbers; (b) traditional logic symbol. Moslem Amiri, Václav Přenosi Design of Digital Systems II Fall, 2014 22 / 69 Decoders: Seven-Segment Decoders Table 10: Truth table for a 74x49 seven-segment decoder. Inputs Outputs BLL D c B A a b c d e f g 0 X X X X 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 0 1 0 0 0 1 0 1 1 0 0 0 0 1 0 0 1 0 1 1 0 1 1 0 1 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1 0 1 0 0 0 0 1 1 0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 0 1 1 1 1 1 0 1 1 0 0 1 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 23 / 69 Decoders: Seven-Segment Decoders • Each output of 74x49 is a minimal POS realization for corresponding segment, assuming don't-cares for non-decimal input combinations • INVERT-OR-AND structure used for each output is equivalent to an AND-OR-INVERT gate, which is a fast and compact structure to build in CMOS or TTL • Modern seven-segment display elements have decoders built into them • A 4-bit BCD word can be applied directly to device Moslem Amiri, Václav Přenosi Design of Digital Systems II Fall, 2014 24 / 69 Decoders: Seven-Segment Decoders Table 11: Verilog program for a seven-segment decoder. module Vr7seg(A, B, C, D, EN, SEGA, SEGB, SEGC, SEGD, SEGE, SEGF, SEGG); input A, B, C, D, EN; output SEGA, SEGB, SEGC, SEGD, SEGE, SEGF, SEGG; reg SEGA, SEGB, SEGC, SEGD, SEGE, SEGF, SEGG; reg [1:7] SEGS; always @ (A or B or C or D or EN) begin if (EN) case ({D,C,B,A}) // Segment patterns abcdefg 0 SEGS = 7'bllllllO // 0 1 SEGS = 7'bOllOOOO // 1 2 SEGS = 7'bllOllOl // 2 3 SEGS = 7'bllllOOl // 3 4 SEGS = 7'bOUOOll // 4 5 SEGS = 7'blOllOll // 5 6 SEGS = 7'bOOlllll // 6 (no 'tail 7 SEGS = 7'bl110000 // 7 8 SEGS = 7'blllllll // 8 9 SEGS = 7'blllOOll // 9 (no 'tail ') ') default SEGS = 7'bx; endcase else SEGS = 7'bO; {SEGA, SEGB, SEGC, SEGD, SEGE, SEGF, SEGG} - SEGS; end endmodule Moslem Amiri, Václav Přenosi Design of Digital Systems II Fall, 2014 25 / 69 Encoders • If a device's output code has fewer bits than input code, it is called an encoder • Simplest encoder to build is a 2"-to-n or binary encoder • Its input code is l-out-of-2" code and its output code is n-bit binary Figure 10: Binary encoder: (a) general structure; (b) 8-to-3 encoder. Y0 = /1 + /3 + /5 + /7 Yl = 12 + 13 + 16 + 17 Y2 = 14 + 15 + 16 + 17 Moslem Amiri, Václav Přenosil Design of Digital Systems II Fall, 2014 26 / 69 Encoders: Priority Encoders • Consider a system with 2" inputs, each of which indicates a request for service • This structure is often found in microprocessor input/output subsystems where inputs might be interrupt requests • Binary encoder works properly only if inputs are guaranteed to be asserted at most one at a time • If multiple requests can be made simultaneously, the encoder gives undesirable results Requests / for service * REQ1 ■ REQ2 ■ REQ3 ■ REQN ■ Requestor's mber Figure 11: A system with 2" requestors, and a "request encoder" that indicates which request signal is asserted at any time. Moslem Amiri, Václav Přenosi Design of Digital Systems II 27 / 69 Encoders: Priority Encoders • We assign priority to input lines, so that when multiple requests are asserted, encoder produces the number of the highest-priority requestor • Such a device is called priority encoder Priority encoder 17 16 A2 15 A1 14 AO 13 12 IDLE 11 10 Figure 12: Logic symbol for a generic 8-input priority encoder. 28 / 69 Encoders: Priority Encoders • Logic equations for priority encoder's outputs (Fig. 12) • Input 17 has the highest priority • Outputs A2-A0 contain number of the highest-priority asserted input • IDLE is asserted if no inputs are asserted • First we define eight intermediate variables H0-H7 • Using AV0-AV7, equations for A2-A0 are similar to ones for a binary encoder H7 = 17 H6 = 16 ■ 17' H5 = 15 ■ 16' ■ 17' HO — 10 ■ II' ■ 12' ■ 13' ■ 14' ■ 15' ■ 16' ■ 17' A2 = HA + H5 + H6 + H7 Al = H2 + AV3 + H6 + H7 AO = HI + AV3 + AV5 + AV7 /DZ.E = /0' • II' ■ 12' ■ 13' ■ I A' ■ 15' ■ 16' ■ 17' 29 / 69 Encoders: The 74x148 Priority Encoder • 74x148 is an MSI 8-input priority encoder 74x148 El I7 I6 A2 I5 A1 I4 AO I3 I2 GS 11 EO I0 Figure 13: Logic symbol for the 74x148 8-input priority encoder. Moslem Amiri, Václav Přenosi Design of Digital Systems II Fall, 2014 30 / 69 Encoders: The 74x148 Priority Encoder Figure 14: Logic diagram for the 74x148 8-input priority encoder, including pin numbers for a standard 16-pin dual in-line package. Moslem Amiri, Václav Přenosi Design of Digital Systems II Fall, 2014 31 / 69 Encoders: The 74x148 Priority Encoder Table 12: Truth table for a 74x148 8-input priority encoder. Inputs Outputs ELL 10-L ll-L I2_L 13-L I4_L 15-L 16-L I7_L A2_L A1_L AO-L GS-L EO_L 1 X X X X X X X X 1 1 1 1 1 0 X X X X X X X 0 0 0 0 0 1 0 X X X X X X 0 1 0 0 1 0 1 0 X X X X X 0 1 1 0 1 0 0 1 0 X X X X 0 1 1 1 0 1 1 0 1 0 X X X 0 1 1 1 1 1 0 0 0 1 0 X X 0 1 1 1 1 1 1 0 1 0 1 0 X 0 1 1 1 1 1 1 1 1 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 Moslem Amiri, Vaclav Prenosil Design of Digital Systems II Fall, 2014 32 / 69 Encoders: The 74x148 Priority Encoder • Instead of an IDLE output, '148 has a GS_L (Group Select) output • It is asserted when device is enabled and one or more of request inputs are asserted • EO_L signal is an enable output used for cascading • It is designed to be connected to ELL input of another '148 that handles lower-priority requests • EO_L is asserted if ELL is asserted but no request input is asserted; thus, a low-priority '148 may be enabled 33 / 69 Encoders: The 74x148 Priority Encoder Figure 15: Four 74x148s cascaded to handle 32 requests. 34 / 69 Encoders: The 74x148 Priority Encoder • In Fig. 15 • There are 32 request inputs and a 5-bit output, RA4-RA0, indicating the highest-priority requestor • Since A2-A0 outputs of at most one '148 will be enabled at any time, outputs of individual '148s can be ORed to produce RA2-RA0 • Individual GS_L outputs can be combined in a 4-to-2 encoder to produce RA4 and RA3 • RGS output is asserted if any GS output is asserted Moslem Amiri, Václav Přenosi Design of Digital Systems II Fall, 2014 35 / 69 Encoders in Verilog Table 13: Behavioral Verilog module for a 74xl48-like 8-input priority encoder. module Vr74xl48(EI_L, I_L, A_L, EO_L, GS_L); input EI_L; input [7:0] I_L; output [2:0] A_L; output E0_L, GS_L: reg [7:0] I; reg [2:0] A, A_L; reg EI, E0_L, EO, GS_L, GS; integer j; always @ (EI_L or EI or I_L or I or A or EO or GS) begin EI = ~EI_L; I = ~I_L; // convert inputs E0_L - "EO; GS_L - "GS; A_L = "A; // convert outputs ED = 1; GS = 0; A = 0; // default output values begin if (EI==0) E0 = 0; else for Cj=0; j<=7; j=j+l) // check low priority first if CI[j]==l) begin GS = 1; E0=0; A = j; end end end endmodule Moslem Amiri, Václav Přenosi Design of Digital Systems II Fall, 2014 36 / 69 Three-State Devices: Three-State Buffers • The most basic three-state device is a three-state buffer, often called a three-state driver ^ ^ ^ (a) (b) (c) (d) Figure 16: Various three-state buffers: (a) non-inverting, active-high enable; (b) non-inverting, active-low enable; (c) inverting, active-high enable; (d) inverting, active-low enable. • When enable input is asserted, device behaves like an ordinary buffer or inverter • When enable input is negated, device output floats • It goes to a high-impedance (Hi-Z), disconnected state and functionally behaves as if it were not even there • Three-state devices allow multiple sources to share a single "party line," as long as only one device talks on the line at a time Moslem Amiri, Václav Přenosil Design of Digital Systems II Fall, 2014 37 / 69 Three-State Devices: Three-State Buffers 1-bit party line EN1 - /EN2 -/EN3 - SSRCO-SSRC1-SSRC2- G1 G2A G2B A B C YO O Y1 O Y2 O Y3 O Y4 O Y5 O Y6 O Y7 O Figure 17: Eight sources sharing a three-state party line. Moslem Amiri, Václav Přenosil Design of Digital Systems II 38 / 69 Three-State Devices: Three-State Buffers • Three-state devices are designed so that they go into Hi-Z state faster than they come out of Hi-Z state • and tpHz are both less than tpzi_ and tpzH • If outputs of two three-state devices are connected to same party line, and we simultaneously disable one and enable other, the first device will get off party line before the second one gets on • If both devices were to drive party line at same time, and if both were trying to maintain opposite output values (0 and 1), then excessive current would flow and create noise in system (fighting) • Delays and timing skews in control circuits make it difficult to ensure that enable inputs of different three-state devices change simultaneously • Even when this is possible, a problem arises if three-state devices from different-speed logic families are connected to same party line » tpZL or tpZH of a fast device may be shorter than tpi_z or tpnz of a slow one Moslem Amiri, Václav Přenosi Design of Digital Systems II Fall, 2014 39 / 69 Three-State Devices: Three-State Buffers » The only safe way to use three-state devices is to design control logic that guarantees a dead time on party line during which no one is driving it • Dead time must be long enough to account for worst-case differences between turn-off and turn-on times of devices and for skews in three-state control signals Figure 18: Timing diagram for the three-state party line of Fig. 17. »™ 7 XX Q XX 1 XX^TT^ U y LT /EN2, /EN3 _J-\_(--\_Pl_/~\_ s data ZB-SZ^fiZB/BZB-SI maxCpLZmax. tpHZmax) — — >X — — min(tpZLmin. pZHmin- dead time Moslem Amiri, Václav Přenosil Design of Digital Systems II Fall, 2014 40 / 69 Three-State Devices: SSI and MSI Three-State Buffers • Each of 74x125 and 74x126 contains four independent non-inverting three-state buffers in a 14-pin package 74x125 Figure 19: Pinouts of the 74x125 and 74x126 three-state buffers. Moslem Amiri, Václav Přenosi Design of Digital Systems II Fall, 2014 41 / 69 Three-State Devices: SSI and MSI Three-State Buffers • Most party-line applications use a bus with more than one bit of data • E.g., in an 8-bit microprocessor system, data bus is eight bits wide, and peripheral devices place data on bus eight bits at a time • A peripheral device enables eight three-state drivers to drive bus, all at the same time • To reduce package size in wide-bus applications, MSI parts contain multiple three-state buffers with common enable inputs Moslem Amiri, Václav Přenosil Design of Digital Systems II Fall, 2014 42 / 69 Three-State Devices: SSI and MSI Three-State Buffers Figure 20: The 74x541 octal three-state buffer: (a) logic diagram, including pin numbers for a standard 20-pin dual in-line package; (b) traditional logic symbol. Moslem Amiri, Václav Přenosi Design of Digital Systems II Fall, 2014 43 / 69 Three-State Devices: SSI and MSI Three-State Buffers Microprocessor DB1 DB2 DB3 DB4 DB5 DB6 DB7 READ INSEL1 DO INSEL2 INSEL3 D1 D2 D3 D4 D5 D6 D7 -O Q1 02 Input Port 1 User . nputs > A1 A2 A3 A4 A5 A6 A7 A8 Y2 Y3 Y4 Y5 Y6 Y7 Y8 -O 01 02 Input Port 2 User . nputs > A1 A2 A3 A4 A5 A6 A7 A8 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 DB[0:7] Figure 21: Moslem Amiri, Václav Přenosi Using a 74x541 as a microprocessor input port. Design of Digital Systems II Fall, 2014 44 / 69 Three-State Devices: SSI and MSI Three-State Buffers • In Fig. 21, microprocessor selects Input Port 1 (top 74x541) by asserting INSEL1 and requests a read operation by asserting READ • Selected 74x541 responds by driving microprocessor data bus with user-supplied input data • Other input ports may be selected when a different INSEL line is asserted along with READ • A bus transceiver contains pairs of three-state buffers connected in opposite directions between each pair of pins, so that data can be transferred in either direction • A bus transceiver is typically used between two bidirectional buses Moslem Amiri, Václav Přenosi Design of Digital Systems II Fall, 2014 45 / 69 Three-State Devices: SSI and MSI Three-State Buffers Figure 22: The 74x245 octal three-state transceiver: (a) logic diagram; (b) traditional logic symbol. 46 / 69 Three-State Devices: SSI and MSI Three-State Buffers Figure 23: Bidirectional buses and transceiver operation. Moslem Amiri, Václav Přenosil Design of Digital Systems II Fall, 2014 47 / 69 Three-State Devices: SSI and MSI Three-State Buffers Table 14: Modes of operation for a pair of bidirectional buses. ENTFFLL ATOB Operation 0 0 Transfer data from a source on bus B to a destination on bus A 0 1 Transfer data from a source on bus A to a destination on bus B 1 X Transfer data on buses A and B independently Moslem Amiri, Václav Přenosil Design of Digital Systems II Fall, 2014 48 / 69 Three-State Devices: Three-State Outputs in Verilog Table 15: Verilog module for a 74x541-like 8-bit three-state driver. module Vr74x540CGl_L, G2_L, A, Y); input G1_L, G2_L; input [1:8] A; output [1:8] Y; assign Y = (~G1_L k ~G2_L) ? A : 8'bz; endmodule Moslem Amiri, Václav Přenosi Design of Digital Systems II Fall, 2014 49 / 69 Three-State Devices: Three-State Outputs in Verilog Table 16: Verilog module for a 74x245-like 8-bit transceiver. module Vr74x245(G_L, DIR, A, B); input G_L, DIR; inout [1:8] A, B; assign A = (~G_L & ~DIR) ? B : 8'bz; assign B = (~G_L k DIR) ? A : 8'bz; endmodule Moslem Amiri, Václav Přenosi Design of Digital Systems II Fall, 2014 Table 17: Verilog module for a four-way, 8-bit bus transceiver. module VrXcvr4x8(A, B, C, D, S, A0E_L, B0E_L, CQE_L, DQE_L, MQE_L) ; input [2:0] S; input ADE_L, B0E_L, C0E_L, DQE_L, K0E_L; inout [1:8] A, B, C, D; reg [1:8] ibus; always © (A or B or C or D or S) begin if (S[2] == 0) ibus = {4{S[1:0]}>; else case CS[1:0]) 0: ibus = A; 1: ibus = B; 2: ibus = C; 3: ibus = D; endcase end assign A assign B assign C assign D C ("AQE_L St C(~B0E_L k CrCOE.L k (C~D0E_L k M0E_L) M.