Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
u1|u0 |
27 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
u1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
u0|system_0_reset_clk_50_domain_synch |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|system_0_reset_clk_domain_synch |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|the_uart_0|the_uart_0_regs |
41 |
10 |
6 |
10 |
41 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
u0|the_uart_0|the_uart_0_rx|the_uart_0_rx_stimulus_source |
15 |
0 |
14 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_uart_0|the_uart_0_rx |
17 |
1 |
0 |
1 |
13 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|the_uart_0|the_uart_0_tx |
25 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_uart_0 |
26 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_uart_0_s1 |
79 |
1 |
18 |
1 |
48 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|the_tri_state_bridge_0_avalon_slave |
72 |
0 |
4 |
0 |
54 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
u0|the_timer_1 |
23 |
0 |
0 |
0 |
17 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_timer_1_s1 |
78 |
1 |
18 |
1 |
44 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|the_timer_0 |
23 |
0 |
0 |
0 |
17 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_timer_0_s1 |
78 |
1 |
18 |
1 |
44 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|the_switch_pio |
22 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_switch_pio_s1 |
46 |
1 |
2 |
1 |
26 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|the_sram_0|the_SRAM_16Bit_512K |
40 |
0 |
1 |
0 |
39 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
u0|the_sram_0 |
40 |
0 |
0 |
0 |
39 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
u0|the_sram_0_avalon_slave_0 |
96 |
1 |
6 |
1 |
68 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|the_sdram_0|the_sdram_0_input_efifo_module |
45 |
0 |
0 |
0 |
45 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_sdram_0 |
45 |
1 |
1 |
1 |
39 |
1 |
1 |
1 |
16 |
0 |
0 |
0 |
0 |
u0|the_sdram_0_s1|rdv_fifo_for_clock_1_out_to_sdram_0_s1 |
7 |
2 |
0 |
2 |
2 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|the_sdram_0_s1|rdv_fifo_for_clock_0_out_to_sdram_0_s1 |
7 |
2 |
0 |
2 |
2 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|the_sdram_0_s1 |
106 |
0 |
2 |
0 |
72 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_led_red |
24 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_led_red_s1 |
61 |
1 |
16 |
1 |
28 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|the_led_green |
15 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_led_green_s1 |
61 |
1 |
25 |
1 |
19 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|the_lcd_16207_0 |
13 |
1 |
1 |
1 |
12 |
1 |
1 |
1 |
8 |
0 |
0 |
0 |
0 |
u0|the_lcd_16207_0_control_slave |
72 |
1 |
29 |
1 |
28 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram|altsyncram2 |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo |
13 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_r |
13 |
0 |
1 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram|altsyncram2 |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo |
13 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_jtag_uart_0|the_jtag_uart_0_scfifo_w |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_jtag_uart_0 |
38 |
10 |
23 |
10 |
36 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
u0|the_jtag_uart_0_avalon_jtag_slave |
97 |
1 |
2 |
1 |
78 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|the_epcs_controller|the_boot_copier_rom|auto_generated |
8 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_epcs_controller|the_tornado_epcs_controller_atom |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|the_epcs_controller|the_epcs_controller_sub |
25 |
0 |
0 |
0 |
23 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_epcs_controller |
46 |
0 |
17 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_epcs_controller_epcs_control_port |
123 |
1 |
4 |
1 |
90 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|the_cpu_0 |
152 |
0 |
23 |
0 |
121 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_cpu_0_instruction_master |
161 |
0 |
3 |
0 |
62 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_cpu_0_data_master |
479 |
23 |
63 |
23 |
116 |
23 |
23 |
23 |
0 |
0 |
0 |
0 |
0 |
u0|the_cpu_0_jtag_debug_module |
125 |
1 |
4 |
1 |
93 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|the_clock_1|endofpacket_bit_pipe |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_clock_1|master_FSM |
5 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_clock_1|write_request_edge_to_pulse |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_clock_1|read_request_edge_to_pulse |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_clock_1|clock_1_slave_write_request_sync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_clock_1|clock_1_slave_read_request_sync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_clock_1|slave_FSM |
6 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_clock_1|write_done_edge_to_pulse |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_clock_1|read_done_edge_to_pulse |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_clock_1|clock_1_master_write_done_sync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_clock_1|clock_1_master_read_done_sync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_clock_1 |
87 |
1 |
0 |
1 |
83 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|the_clock_1_out |
66 |
0 |
19 |
0 |
41 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_clock_1_in |
70 |
2 |
3 |
2 |
91 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|the_clock_0|endofpacket_bit_pipe |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_clock_0|master_FSM |
5 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_clock_0|write_request_edge_to_pulse |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_clock_0|read_request_edge_to_pulse |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_clock_0|clock_0_slave_write_request_sync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_clock_0|clock_0_slave_read_request_sync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_clock_0|slave_FSM |
6 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_clock_0|write_done_edge_to_pulse |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_clock_0|read_done_edge_to_pulse |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_clock_0|clock_0_master_write_done_sync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_clock_0|clock_0_master_read_done_sync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_clock_0 |
87 |
17 |
0 |
17 |
83 |
17 |
17 |
17 |
0 |
0 |
0 |
0 |
0 |
u0|the_clock_0_out |
66 |
0 |
19 |
0 |
41 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_clock_0_in |
49 |
4 |
3 |
4 |
73 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
u0|the_button_pio |
14 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_button_pio_s1 |
66 |
1 |
30 |
1 |
19 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|the_VGA_0|the_VGA_NIOS_CTRL|u1|u0|altsyncram_component|auto_generated|altsyncram1|mux6 |
82 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_VGA_0|the_VGA_NIOS_CTRL|u1|u0|altsyncram_component|auto_generated|altsyncram1|mux5 |
607 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_VGA_0|the_VGA_NIOS_CTRL|u1|u0|altsyncram_component|auto_generated|altsyncram1|decode_b |
8 |
1 |
0 |
1 |
75 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|the_VGA_0|the_VGA_NIOS_CTRL|u1|u0|altsyncram_component|auto_generated|altsyncram1|decode_a |
8 |
1 |
0 |
1 |
75 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|the_VGA_0|the_VGA_NIOS_CTRL|u1|u0|altsyncram_component|auto_generated|altsyncram1|decode4 |
8 |
0 |
0 |
0 |
75 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_VGA_0|the_VGA_NIOS_CTRL|u1|u0|altsyncram_component|auto_generated|altsyncram1|decode3 |
8 |
0 |
0 |
0 |
75 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_VGA_0|the_VGA_NIOS_CTRL|u1|u0|altsyncram_component|auto_generated|altsyncram1 |
49 |
9 |
1 |
9 |
8 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
u0|the_VGA_0|the_VGA_NIOS_CTRL|u1|u0|altsyncram_component|auto_generated |
39 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_VGA_0|the_VGA_NIOS_CTRL|u1|u0 |
39 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_VGA_0|the_VGA_NIOS_CTRL|u1 |
103 |
0 |
0 |
0 |
30 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_VGA_0|the_VGA_NIOS_CTRL|u0 |
86 |
2 |
0 |
2 |
55 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|the_VGA_0|the_VGA_NIOS_CTRL |
41 |
0 |
0 |
0 |
51 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_VGA_0 |
41 |
0 |
0 |
0 |
51 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_VGA_0_avalon_slave_0 |
76 |
1 |
18 |
1 |
61 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|the_SEG7_Display|the_SEG7_LUT_8|u7 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_SEG7_Display|the_SEG7_LUT_8|u6 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_SEG7_Display|the_SEG7_LUT_8|u5 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_SEG7_Display|the_SEG7_LUT_8|u4 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_SEG7_Display|the_SEG7_LUT_8|u3 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_SEG7_Display|the_SEG7_LUT_8|u2 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_SEG7_Display|the_SEG7_LUT_8|u1 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_SEG7_Display|the_SEG7_LUT_8|u0 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_SEG7_Display|the_SEG7_LUT_8 |
35 |
0 |
0 |
0 |
56 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_SEG7_Display |
35 |
0 |
0 |
0 |
56 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_SEG7_Display_avalon_slave_0 |
60 |
1 |
2 |
1 |
39 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|the_SD_DAT |
7 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
u0|the_SD_DAT_s1 |
62 |
1 |
33 |
1 |
12 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|the_SD_CMD |
7 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
u0|the_SD_CMD_s1 |
62 |
1 |
33 |
1 |
12 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|the_SD_CLK |
7 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_SD_CLK_s1 |
61 |
1 |
33 |
1 |
11 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|the_ISP1362|the_ISP1362_IF |
25 |
0 |
0 |
0 |
24 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
u0|the_ISP1362 |
25 |
0 |
0 |
0 |
24 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
u0|the_ISP1362_avalon_slave_1 |
3 |
0 |
2 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_ISP1362_avalon_slave_0 |
77 |
1 |
18 |
1 |
46 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|the_DM9000A|the_DM9000A_IF |
24 |
0 |
0 |
0 |
23 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
u0|the_DM9000A |
24 |
0 |
0 |
0 |
23 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
u0|the_DM9000A_avalon_slave_0 |
77 |
1 |
18 |
1 |
45 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|the_Audio_0|the_AUDIO_DAC_FIFO|u0|dcfifo_component|auto_generated|wrfull_eq_comp |
18 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_Audio_0|the_AUDIO_DAC_FIFO|u0|dcfifo_component|auto_generated|rdempty_eq_comp |
18 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_Audio_0|the_AUDIO_DAC_FIFO|u0|dcfifo_component|auto_generated|ws_dgrp|dffpipe20 |
11 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_Audio_0|the_AUDIO_DAC_FIFO|u0|dcfifo_component|auto_generated|ws_dgrp |
11 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_Audio_0|the_AUDIO_DAC_FIFO|u0|dcfifo_component|auto_generated|rs_dgwp|dffpipe17 |
11 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_Audio_0|the_AUDIO_DAC_FIFO|u0|dcfifo_component|auto_generated|rs_dgwp |
11 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_Audio_0|the_AUDIO_DAC_FIFO|u0|dcfifo_component|auto_generated|rdaclr |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|the_Audio_0|the_AUDIO_DAC_FIFO|u0|dcfifo_component|auto_generated|fifo_ram|altsyncram14 |
56 |
17 |
0 |
17 |
16 |
17 |
17 |
17 |
0 |
0 |
0 |
0 |
0 |
u0|the_Audio_0|the_AUDIO_DAC_FIFO|u0|dcfifo_component|auto_generated|fifo_ram |
38 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_Audio_0|the_AUDIO_DAC_FIFO|u0|dcfifo_component|auto_generated|wrptr_gp |
3 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_Audio_0|the_AUDIO_DAC_FIFO|u0|dcfifo_component|auto_generated|wrptr_g1p |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_Audio_0|the_AUDIO_DAC_FIFO|u0|dcfifo_component|auto_generated|rdptr_g1p |
3 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_Audio_0|the_AUDIO_DAC_FIFO|u0|dcfifo_component|auto_generated |
21 |
0 |
0 |
0 |
17 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_Audio_0|the_AUDIO_DAC_FIFO|u0 |
21 |
0 |
0 |
0 |
17 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_Audio_0|the_AUDIO_DAC_FIFO |
20 |
15 |
0 |
15 |
20 |
15 |
15 |
15 |
0 |
0 |
0 |
0 |
0 |
u0|the_Audio_0 |
20 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|the_Audio_0_avalon_slave_0 |
77 |
1 |
18 |
1 |
39 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0 |
32 |
0 |
0 |
0 |
208 |
0 |
0 |
0 |
82 |
0 |
0 |
0 |
0 |
PLL2 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
PLL1 |
1 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
delay1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |