VHDL
Zdeněk Matěj
72963@mail.muni.cz
VHDL
VHSIC (Very High Speed Integrated
Circuit)
Hardware
Description
Language
Structure
 Construction blocks
 Entity
 Describes a module's interface
 Architecture
 Behavioral description of the block
ARCHITECTURE
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ENTITY
Entity
 Describes interface of latch - it's inputs and outputs
entity latch is -- Use double dash for a comment
port ( s,r: in bit;
q,nq: out bit);
end latch;
 Input and output signals are marked with in and out (we can also
use inout)
Architecture
 Represents a behavioral description's instance
 Generally, one entity may have multiple architectures
architecture dataflow of latch is – archictecture's name is dataflow
begin
q<=r nor nq; -- operator <= assigns signal
nq<=s nor q; -- function „nor“ has been defined
end dataflow;
Component
 We use it for module's instantiation
entity latch is
port (s,r: in bit;
q,nq: out bit);
end latch;
architecture structure of latch is
component nor_gate
port (a,b: in bit;
c: out bit); -- make sure you keep the ports' order:- in,in,out
end component;
begin
n1: nor_gate
port map (r,nq,q); -- component ports are assigned to given signals in the parent architecture
n2: nor_gate
port map (s,q,nq);
end structure;
Assignments
 VHDL is strongly typed and there are no automatic type casts like
in C language
 Signal
 a<=b and c;
 Variable
 v:=a + 2;
Process
 It allows us to create a structured description of architecture
process (b,c) -- process is executed whenever b or c changes
begin
a<=b xor c;
end process;
Variables
 Used exclusively inside a process block
count: process (x)
variable cnt : integer := -1;
begin
cnt:=cnt + 1;
end process;
 Before first process execution, value of cnt will be initialized as 0
Variables - cont.
 For data types, we can use integer, bit, etc. (see the
documentation)
 However, for signal we use STD_LOGIC data type
 Example of vector definition: std_logic_vector(0 to 17);
Sequential expressions
 Can be created exclusively inside a process
count: process (x)
variable cnt : integer :=0 ;
begin
if (x='1' and x'last_value='0') then
cnt:=cnt + 1;
end if;
end process;
 last_value stands for latest value of variable x before invoking the
process
 Another sequential constructions can be examinated in the
documentation
Signals
 Signals are local for an architecture and can't be accessed from
outside
 All assignments to signals are performed after the whole process
body is finished
signal x,y,z : bit;
...
process (y) -- change of y starts the process
begin
x<=y;
end process;
Comparison of VHDL and Verilog
Comparison of VHDL and Verilog
Literature
 https://l202.fi.muni.cz/vyuka/pv200/materialy
 HDL chip design – Douglas J. Smith
 Altera: http://www.altera.com/support/examples/vhdl/vhdl.html
 http://esd.cs.ucr.edu/labs/tutorial/
 http://www.angelfire.com/in/rajesh52/verilogvhdl.html
 http://en.wikipedia.org/wiki/VHDL
Tasks
 Task no. 1
 Describe 4-bit adder in VHDL, use LEDs and SWITCHes
 Task no. 2
 Describe RS circuit in VHDL, use two KEYs and LED to
indicate the current state.
 Task no. 3
 Describe clock divider in VHDL in a separate module and use
the module's instance in another module (e.g., in top module).
Propagate divided clock signal to a LED.