library ieee;
use ieee.std_logic_1164.all;


entity clk_div is
    generic (
        div: integer := 4
    );
    port (
        clk: in std_logic;
        rst: in std_logic;

        clk_div: out std_logic
    );

end clk_div;


architecture behavior of clk_div is
begin

    process (clk, rst)
        variable clk_div_reg: std_logic;
        variable cnt: integer;
    begin
        if (rising_edge(clk)) then
            if (rst = '1') then
                clk_div_reg := '0';
                cnt := 0;
            else
                if (cnt = div - 1) then
                    clk_div_reg := not clk_div_reg;
                    cnt := 0;
                else
                    cnt := cnt + 1;
                end if;
                clk_div <= clk_div_reg;
            end if;
        end if;
    end process;

end;