VHDL Syntax Reference
By Prof. Taek M. Kwon
EE Dept, University of Minnesota Duluth
This summary is provided as a quick lookup resource for VHDL syntax and code examples. Please click on the topic you are looking for to jump to the corresponding page.
Contents
1. Bits, Vectors, Signals, Operators, Types
1.1 Bits and Vectors in Port....................
1.2 Signals...............................................
1.3 Constants..........................................
1.4 Relational Operators.........................
1.5 Logical Operators......................................................................................................2
1.6 Assignments..............................................................................................................2
1.7 Concatenation, &......................................................................................................3
1.8 Type Conversion Chart.............................................................................................3
2. Concurrent Statements....................................................................................................4
2.1 Conditional Signal Assignment................................................................................4
2.2 Selected Signal Assignment......................................................................................5
3. Sequential Statements.....................................................................................................5
3.1 Variables...................................................................................................................5
3.2 If-then-else Statement...............................................................................................6
3.3 Case Statement..........................................................................................................6
3.4 For Loop....................................................................................................................7
3.5 While Loop...............................................................................................................8
3.6 Infinite Loop.............................................................................................................8
3.7 Wait Statements........................................................................................................8
3.8 Finite State Machine (FSM) Implementation...........................................................9
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1. Bits, Vectors, Signals, Operators, Types
1.1 Bits and Vectors in Port
Bits and vectors declared in port with direction. Example:
port ( a : in std_logic; — signal comes in to port a from outside b : out std_logic; — signal is sent out to the port b c : inout std_logic; — bidirectional port x : in std_logic_vector(7 downto 0); - 8-bit input vector y : out std_logic_vector(7 downto 0) - no ';' for the last item
);
1.2 Signals
Signals are declared without direction.
Example:
signal si, s2 : std_logic;
signal X, Y : std_logic_vector(31 downto 0);
1.3 Constants
Constants are useful for representing commonly-used values of specific types.
Example:
In the declaration area:
constant init: std_logic_vector(3 downto 0) := "1100"; signal sig_vec : std_logic_vector(3 downto 0);
In the body: sig_vec <= init;
1.4 Relational Operators
Return a Boolean result and thus used in if or when clauses.
= equal to: highest precedence
1= not equal to
< less than
<= less than equal
> greater than
>= greater than equal: lowest precedence
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1.5 Logical Operators
Bit-by-bit logical operations.
not example) (not a) highest precedence
and
or
nand
nor
xor
xnor lowest precedence
1.6 Assignments
<= signal assignment
:= variable assignment, signal initialization
Example:
signal q: std_logic_vector(3 downto 0);
Multiple bits are enclosed using a pair of double quotations: q <= "1011";
Hexadecimals are represented using X"....": q <= X"B";
A single bit is enclosed using single quotations: q<= ('l\'0\'l\'l');
You may use named association: q<= (3=>'1',2=>'0\ 1=>'1',0=>'1');
Named association allows position independence, i.e., you can write q <= (0=>'1\ 2=>'0\ 1=>'1\ 3=>'l');
You may combine indices. q<= (3|1|0=>'1\2=>'0');
Use the keyword 'others' to simplify the expression. q<= (2=>'0\ others =>'l');
We frequently use others for initialization or setting bits, x <= "00000000";     - is same as x<= (others => '0');
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1.7 Concatenation, &
Example: signal a, b : std_logic_vector(7 downto 0) := "10111111"; b <= a(7 downto 2) & "00"; - b contains "10111100"
1.8 Type Conversion Chart
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2. Concurrent Statements
Any statement placed in architecture body is concurrent. Only one type of conditional statements is allowed as concurrent which are shown here.
2.1 Conditional Signal Assignment
Syntax:
signal_name <= value_expr_l when Boolean_expr_l else value_expr_2 when Boolean_expr_2 else value_expr_3 when Boolean_expr_3 else
value_expr_n;
Example: 4-to-l Mux
z <= a when (s="00") else
b when (s="01") else cwhen (s=" 10") else dwhen (s="ll") else
'X';
a
b
c
4-to-1 Mux
Z
d
A better way would be:
s1
sO
z <= a when (s="00") else
b when (s="01") else cwhen (s="10") else d;
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2.2 Selected Signal Assignment
Syntax:
with select_expression select
signal_name <= value_expr_l when choice_l, value_expr_2 when choice_2,
value_expr_n when choice_n;
Example: 4-to-l Mux
with s select
z <= a when "00", b when "01", cwhen "10", d when others;
3. Sequential Statements
3.1 Variables
Variables are objects used to store intermediate values between sequential VHDL statements. Variables are only allowed in processes, procedures and functions, and they are always local to those functions. When a value is assigned to a variable, ":=" is used.
Example:
signal Grant, Select: std_logic;
process(Rst, Clk)
variable Ql, Q2, Q3: stdjogic; begin
ifRst='l' then
Ql :='0'; Q2:='0'; Q3 :='0'; elsif (Clk='l' and Clk'event) then Ql := Grant; Q2 := Select; Q3 := Ql or Q2; end if; end process;
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Note: Both signals and variables carry data from place to place. However, you must always use signals to carry information between concurrent elements of your design.
3.2 If-then-else Statement
Syntax:
if Boolean_expr_l then
sequential_statements;
elsif Boolean_expr_2 then
sequential_statements;
elsif Boolean_expr_3 then
else
sequential statements;
end if;
Example:
process ( a, b, m, n) begin
if m = n then
r <= a + b; elsif   m > 0 then
r <= a - b;
else
r <= a + 1;
end if;
end;
3.3 Case Statement
Syntax:
case sel is
when choice_l =>
sequential_statements; when choice_2 =>
sequenti al_statements;
when others =>
sequential_statements;
end case;
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Example:
case sel is
when "00" =>
r <= a + b; when "10"
r <= a - b; when others =>
r <= a + 1;
end case;
3.4 For Loop
Syntax:
for index in loop_range loop sequential statements; end loop;
Example:
constant MAX: integer := 8;
signal a, b, y: std_logic_vector(MAX-l downto 0);
for i in (MAX-1) downto 0 loop
y(i) <= a(i) xor b(i) end loop;
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3.5 While Loop
Syntax:
loop_name: while (condition) loop
—repeated statements end loop loop_name;
Example:
while error_flag /= ' 1' and done /=' 1' loop
Clock <= not Clock;
wait for CLK_PERIOD/2; end loop;
3.6 Infinite Loop
Syntax:
loop_name: loop
exit when (condition) end loop loop_name;
Example:
loop
Clock <= not Clock;
wait for CLK_PERIOD/2;
if done = ' 1' or error flag = ' 1' then
exit; end if; end loop;
3.7 Wait Statements
wait on signals;
wait until Boolean_expr;
wait for time_expr;
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3.8 Finite State Machine (FSM) Implementation
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Finite state machines in VHDL can be implemented by following a typical programming structure such as given below. It consists of two processes: one for combinational logic process that sets the next state and output, and a clock handling process that loads the next state to present state. This implementation is a Mealy machine.
Entity state_machine is Port( reset, elk, x: in std_logic;
Z: out std_logic); End state_machine;
—Architecture portion of the code is shown in the next page.
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Architecture bhv of state_machine is
Type statetype is (stateO, statel); — define states Signal Pstate, Next_state: statetype;
Begin
Logic_proc: process(pstate, x) Begin
Case pstate is
When stateO => If x='0' then
Next_state < Z<= '1';
Else
Next_state <
Z<='0'; End if; When statel => Ifx='l' then
Next_state <
Z<= '0';
Else
Next_state < Z<= T; End if; End case; End process Logic_proc;
Clock_proc: process Begin
Wait until (clk'event and elk =' 1'); If reset = ' 1' then
Pstate <= statetype'left; Else
Pstate <= next_state; End if; End process Clock_proc;
End bhv;
= state 1; = stateO;
= stateoO; = state 1;
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