---
author: Oldrich Pecak
---

# Verilog - intro

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## Sequential -> ROM

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## Verilog

- hardware description language
- subset of SystemVerilog
- similar languages: VHDL, Clash

```verilog
module xor_module(input a, input b, output reg c);
    always @(*) begin
        c <= a ^ b;
    end
endmodule
```

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## Toolchain

- Verilog inside Digital
- Icarus Verilog (IVerilog)
    - Verilog compiler
- GTKWave
    - simulation output viewer
- lot of proprietary manufacturer tools

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## Variables, nets, registers

```verilog
wire a;
wire b[3:0];

reg c;
reg d[3:0];

d <= 4'b0011;
d <= 4'hf;
d <= 4'd12;

assign b = d;
```

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## Operators, assignments

- all common operators from C++
- two assignment types

```verilog
wire a[1:0];
reg b[4:0];

if (a >= 2'b10) begin
    b <= 4'b1010;
end else begin
    b = 4'b1111;
end

```

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## Modules

- basic building blocks

```verilog
module my_first_module(
    input a[3:0],
    input reg b,
    input clk,
    output c[2:0]
);

always @(posedge clk) begin
    // blablabla logic here
end

endmodule

//instantiation

wire x[7:0];
wire y, z;
wire c[4:0];

my_first_design mod(x[5:2], y, z, w[2:0]);
```

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## Processes

- also called sensitivity blocks
- define when to actually trigger the logic

```
always @(posedge clk or negedge rst) begin
    // logic A
end

always @*  //triggers on any change

initial //triggers only once at start

```

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## Let's try it!

- build basic XOR in Digital using Verilog

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## Let's try it!

- build basic XOR in Digital using Verilog
- build a 4bit multiplexer

---

## Let's try it!

- build basic XOR in Digital using Verilog
- build a 4bit multiplexer
- build following sequential logic
    - pulse length counter (min length of 3 cycles)
    - /8 clock divider
    - 16x8bit memory