FI:PV200 HW description languages I - Course Information
PV200 Introduction to hardware description languages
Faculty of InformaticsAutumn 2024
- Extent and Intensity
- 0/2/1. 3 credit(s) (plus extra credits for completion). Type of Completion: k (colloquium).
In-person direct teaching - Teacher(s)
- Ing. Jiří Čulen (lecturer)
prof. Ing. Václav Přenosil, CSc. (alternate examiner)
doc. RNDr. Zdeněk Matěj, Ph.D. (lecturer) - Guaranteed by
- doc. RNDr. Zdeněk Matěj, Ph.D.
Department of Computer Systems and Communications – Faculty of Informatics
Contact Person: doc. RNDr. Zdeněk Matěj, Ph.D.
Supplier department: Department of Computer Systems and Communications – Faculty of Informatics - Timetable of Seminar Groups
- PV200/01: Thu 26. 9. to Thu 19. 12. Thu 16:00–17:50 A415, J. Čulen, Z. Matěj
PV200/02: Thu 26. 9. to Thu 19. 12. Thu 18:00–19:50 A415, J. Čulen, Z. Matěj - Course Enrolment Limitations
- The course is also offered to the students of the fields other than those the course is directly associated with.
- fields of study / plans the course is directly associated with
- there are 32 fields of study the course is directly associated with, display
- Course objectives
- Within this course the students will obtain deeper knowledge on the field-programmable gate array (FPGA) and get familiar with advanced methods of hardware design using hardware description languages (HDL). Verilog HDL is used to demonstrate most of the principles.
- Learning outcomes
- Graduates of this course will be able to:
understand the FPGA principle;
design advanced systems using HDL Verilog version 2001
design application for FPGA. - Syllabus
- Programmable structures fundamentals.
- Structural modelling of programable logic using schematics, basics of simulations.
- Verilog HDL – concepts, basic syntax, structural modelling, design hierarchy.
- Behavioural modelling of combinational logic, decoders, adders, subtractors.
- Simulations by ModelSim, using of test benches
- Sequential logic - Counters, clock dividers
- Sequential logic – Synchronous design
- Sequential logic – Finite state machines
- Introduction to System Verilog and VHDL.
- Practical tasks in Quartus II suite.
- Literature
- Teaching methods
- Laboratory seminar.
- Assessment methods
- The evaluation consists of:
a) defense of a set of tasks submitted during semester
b) defense of final project. - Language of instruction
- English
- Follow-Up Courses
- Further comments (probably available only in Czech)
- Study Materials
The course is taught annually. - Teacher's information
- The course takes place in the EmLab - A415.
- Enrolment Statistics (recent)
- Permalink: https://is.muni.cz/course/fi/autumn2024/PV200